A Scalable Design Approach to Efficiently Map Applications on CGRAs

Abstract

Coarse-Grained Reconfigurable Architectures (CGRAs) are promising high-performance and power-efficient platforms. However, their uses are still limited because of the current capability of the mapping tools. This paper presents a new scalable efficient design flow to map applications written in high level language on CGRAs. This approach leverages on simultaneous scheduling and binding steps respectively based on a heuristic and an exact method stochastically degenerated. The formal graph model of the application, obtained after compilation, is backward traversed and dynamically transformed when needed to allow for a better exploration of the design space. Results show that our approach is scalable, finds most of the time the best solutions i.e. the mappings with the shortest latencies, achieves lowest failure rate in carrying out solutions, provides lower computation time and explores more efficiently the solution space than the state of the art methods.

An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing

“…This is ensured by the register allocation approach. To map the basic blocks, we rely on the highly scalable and efficient mapping approach for DFGs described in [8]. The compilation flow proposed in this paper, extends the DFG mapping to accommodate the register allocation approach to map a full CDFG onto the PE array.…”

“…And it grows exponentially if not pruned. Hence, we use the stochastic pruning approach described in [8].…”

Generic Connectivity-Based CGRA Mapping via Integer Linear Programming

“…While the ILP and SAT methods mentioned above try to solve placement and routing at the same time, this work splits them up somewhat, like [5], [14], [17], [18] or typical FPGA mapping approaches. The aim is to break-up one intractable problem into smaller tractable problems, but CGRAs have resisted this by having inflexible routing, as evidenced by the long runtimes of [5], [17].…”

“…This approach is influenced by [9], [19]- [22], in that it primarily operates on connectivity information, but these other mapping procedures are each tuned/designed for a specific class of architectures. The methods of [14], [18]- [20] manipulate the DFG to assist in mapping the architectures (such as node duplication, and adding explicit "routing" nodes). To remain generic, we hesitate to manipulate the DFG, instead allowing scheduling to be decided as part of the placement.…”

Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs

“…The mapping approach must travel each basic block, and for each block, it must find a valid mapping of the dataflow graph. The way the control flow and the data flow are traversed has an influence on the quality of the resulting mapping [1], [2]. When a valid mapping is found, the compiler generates the assembly code for each tile, which will be placed in the context memory.…”