A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design

Hu, Yu; Tong, Jing; Hong, Xianlong; Hu, Xiaodong; Ge, Yan

doi:10.1007/11512622_37

Cited by 7 publications

(8 citation statements)

References 19 publications

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“…As the placement tool in X-Architecture is not mature [1], we utilize the placement result of a traditional standard cell placer as the input of our global router. We adopt the GRG partition method in [10]. As Fig.1 shows, we add some diagonal edges to connect each two diagonal adjacent vertices.…”

Section: A Grg Generation In X-architecturementioning

confidence: 99%

“…To demonstrate the optimization capability of our router, we compare our router with x-labyrinth and COCO [10]. For a fare comparison, we assign the same routing resources to all the three routers.…”

Section: A Experiments Setupmentioning

confidence: 99%

“…Liquid routing model [1], [18] is an effective way to reduce vias in X-Architecture. [10] considers the liquid routing model in global routing phase, and studies on the routing resource estimation method for liquid routing model in X-Architecture, based on which a global routing algorithm is presented. Compared with labyrinth [3] and SSTT [12] in Manhattan architecture, this algorithm can reduce the total wire length and total overflow more than 10% and 80% on average, respectively.…”

Section: Introductionmentioning

confidence: 99%

“…At the same time, the runtime of DraXRouter is 33% shorter. Compared with COCO algorithm [10], DraXRouter gains a better routing result with an acceptable runtime. Meanwhile, we compared the wire crossover in the global routing results produced by DraXRouter with the traditional resources assignment (RA) methods and that with the Dra method, respectively.…”

Section: Introductionmentioning

confidence: 99%

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DraXRouter

Cao¹,

Tong²,

Hu³

et al. 2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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In recent years, the X-Architecture is introduced to obtain better performance for integrated circuit physical design. This paper reformulates the global routing problem in X-Architecture under the liquid routing model. Then, a dynamic resource assignment (Dra) method is presented to reduce potential vias. At last, a global router called DraXRouter, is designed, in which we adopt a dynamic-tabulist-based tree construction algorithm and a stochastic optimization strategy to gain high quality routing solution. Tested on ISPD'98 benchmarks, DraXRouter achieves better routing performance compared with two recent global routers. 1 We designed labyrinth algorithm [7] in X-Architecture, called x-labyrinth, for more comparison with our DraXRouter.

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Section: A Grg Generation In X-architecturementioning

confidence: 99%

Section: A Experiments Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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DraXRouter

Cao¹,

Tong²,

Hu³

et al. 2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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“…This leads to reduced routing flexibility compared to non-manhattan routing. To overcome this limitation, a new routing paradigm allowing wires to route at 45° and 135° directions, called X architecture has been proposed [21,22].…”

Section: Introductionmentioning

confidence: 99%

Ant Colony Optimization for power efficient routing in manhattan and non-manhattan VLSI architectures

Arora

Moses

2009

2009 IEEE Swarm Intelligence Symposium

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Abstract-Rapid advances in VLSI technology have increased the number of transistors that fit on a single chip to about two billion. In such complex designs, a primary design goal is to limit the power consumption of the chip. Power consumption depends on capacitance, which depends on the length of wires on the chip and the number of vias which connect wires on different layers of the chip. We use Ant Colony Optimization (ACO) algorithms to minimize wirelength, vias and capacitance. ACO provide a multi-agent framework for combinatorial optimization by combining memory, stochastic decision making and strategies of collective and distributed learning by ant-like agents. This paper applies ACO to the NP-hard problem of finding optimal routes with minimum capacitance for interconnect routing on VLSI chips. The constraints on interconnect routing are used by ants as heuristics which guide their search process. We implemented ACO algorithms on both manhattan and non-manhattan routing architectures. The results are compared with several state of the art academic routers. The ACO routing algorithm was able to obtain an overall improvement of 9% in terms of wire-length, 7% in terms of vias and 18% in terms of capacitance. Running times were longer than those routers, but very similar to the other router which is able to route all wires on all benchmark chips.

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Steiner Minimal Trees in Rectilinear and Octilinear Planes

Shang

Tong

2007

Acta Math Sinica

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A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design

Cited by 7 publications

References 19 publications

DraXRouter

DraXRouter

Ant Colony Optimization for power efficient routing in manhattan and non-manhattan VLSI architectures

Steiner Minimal Trees in Rectilinear and Octilinear Planes

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