Ant Colony Optimization for power efficient routing in manhattan and non-manhattan VLSI architectures

Arora, Tamanna; Moses, Melanie E.

doi:10.1109/sis.2009.4937856

Cited by 16 publications

(7 citation statements)

References 32 publications

(40 reference statements)

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“…ACO-Steiner can be easily extended to other routing problems such as power-driven routing. References [49] and [50] implement ACO algorithms on both grid-less Manhattan architectures and non-Manhattan routing architectures that use diagonal routing, which aim at limiting the power consumption of the chip. The difference is that, [50] actives power on the chip not only by minimizing wirelength and vias, but also capacitance.…”

Section: ) Applying Aco To Global Routingmentioning

confidence: 99%

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

et al. 2020

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Routing is a complex and critical stage in the physical design of Very Large Scale Integration (VLSI), minimizing interconnect length and delay to optimize overall chip performance. With the rapid development of modern technology, VLSI routing faces enormous challenges such as large delay, high congestion, and high-power consumption. As a rising optimization method, Swarm Intelligence (SI) inspired from collective intelligence behaviors through cooperation or interaction with the environment provides effectiveness and robustness for solving NP-hard problems. Many researchers have consequently used SI techniques to solve routing-related problems in VLSI. This paper reviews the application of several SI techniques to the VLSI routing filed. Firstly, five commonly used SI techniques and related models, and three classic routing problems are described: Steiner tree construction, global routing and detailed routing. Then an overview of the current state of this field is given according to the above categories, and the survey offers informative discussions from five aspects: 1) Steiner minimum tree construction; 2) wirelength-driven routing; 3) obstacle-avoiding routing; 4) timing-driven routing; 5) power-driven routing. Finally, under three new technology models: X-architecture, multiple dynamic supply voltage and via-pillar, the future development trends are pointed as follows: 1) suggesting suitable SI techniques to specific routing problems for advanced technology models; 2) exploring new and available SI techniques that have not yet been applied to VLSI routing.

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Section: ) Applying Aco To Global Routingmentioning

confidence: 99%

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

et al. 2020

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“…As Swarm Intelligence algorithms have been shown to have good application prospects in solving NP-hard problems, Arora et al proposed an algorithm based on ACO in [148]. The combination of ant colony learning strategies provides a multi-agent framework for combinatorial optimization.…”

Section: ) Power-driven Routingmentioning

confidence: 99%

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

et al. 2020

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Global Routing (GR) is a crucial and complex stage in the Very Large-Scale Integration (VLSI) design, which minimizes interconnect wirelength and delay to optimize the overall chip performance. Steiner tree construction is one of the basic models of VLSI physical design, which is usually used in the initial topology creation for noncritical nets in physical design. In a GR process, a Steiner Minimum Tree (SMT) algorithm can be invoked millions of times, which means that SMT algorithm has great significance for the final quality of GR. Some of the research works are surveyed in this paper to understand GR and SMT problems and to learn the available solutions. Firstly, we systematically dissect three types of subproblems in Steiner tree construction and three types of GR methods. Then, we investigate the recent progress under two new technology models. Finally, the survey concludes with a summary of possible future research directions.

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“…Many other technique based on SI has been used for escalation of VLSI routing, among them the one proposed by Arora and Moses is important. Both Manhattan as well as a non-Manhattan routing scheme based on Ant Colony Optimization (ACO) [11] were proposed by the duo. A proposal was introduced by Ayob et al to evade VLSI routing scheme by using Firefly optimization [12].…”

Section: Introductionmentioning

confidence: 99%

Performance Comparison of PSO and Its New Variants in the Context of VLSI Global Routing

Nath¹,

Sing²,

Sarkar³

2018

Particle Swarm Optimization With Applications

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Substantial reduction of gate delay occurred in recent times owing to radical decrement of transistor size. The interconnect length and delay are accordingly increased owing to the exponential escalation of packaging density with additional transistors being fabricated on the same chip area. The function of VLSI routing that seems to be more defying to the scholars, is categorized in global routing and detailed routing phase. In global routing phase, the prevalent method to lessen the wire length for reducing interconnect delay is to adjust the cost of the Steiner tree, devised by the terminal nodes to be interconnected. Nevertheless, Steiner tree problem is a NP-complete problem in classical graph theory where meta-heuristics might impart beneficial elucidations. Particle swarm optimization (PSO) is a robust algorithm concerning VLSI routing field. This chapter is regarding the proposal of a self-adaptive mechanism for monitoring acceleration coefficient of PSO and evaluating its functionalities with the existing acceleration coefficient controlled PSO in numerous allocation topologies of terminal nodes within definite VLSI layout. The outcomes of PSO variant with constriction factor in context to VLSI route reduction ability and robustness are also inspected. Additionally, a new effort in adapting the PSO with embracement of genetic algorithm is established.

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Ant Colony Optimization for power efficient routing in manhattan and non-manhattan VLSI architectures

Cited by 16 publications

References 32 publications

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

A Survey on Steiner Tree Construction and Global Routing for VLSI Design

Performance Comparison of PSO and Its New Variants in the Context of VLSI Global Routing

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