A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

Bjerregaard, Tobias; Sparsø, Jens

doi:10.1109/date.2005.36

Cited by 226 publications

(131 citation statements)

References 16 publications

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“…The commercial startup Silistix, based on earlier academic research [10], sells EDA software and circuits that provide an customized asynchronous NoC, but has no published methods for the optimization process. The MANGO router [11] provides both best-effort and guaranteed-service traffic. FAUST [12] is a platform and fabricated chip used in 4G telephony development, and uses an asynchronous mesh-based NoC [13].…”

Section: Related Workmentioning

confidence: 99%

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Gebhardt

You

Stevens

2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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Abstract-Power consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous networkon-chip implementations, optimized for a number of SoC designs. We adapted the COSI-2.0 framework with ORION 2.0 router and wire models for synchronous network generation. Our own tool, ANetGen, specifies the asynchronous network by determining the topology with simulated-annealing and router locations with force-directed placement. It uses energy and delay models from our 65 nm bundled-data router design. SystemC simulations varied traffic burstiness using the self-similar b-model. Results show that the asynchronous network provided lower median and maximum message latency, especially under bursty traffic, and used far less router energy with a slight overhead for the interrouter wires.

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Section: Related Workmentioning

confidence: 99%

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Gebhardt

You

Stevens

2010

2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

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“…It also indicates that for small applications, a feature rich NoC [11,4,3,7] takes up too much area and uses too much power. We believe there are a large number of current, and future, applications for which a simple NoC is a feasible solution.…”

Section: Resultsmentioning

confidence: 99%

“…This leads to fairly large and feature rich NoCs, providing large amount of bandwidth and advanced Quality-of-Service (QoS) features. Examples of such NoCs are Nostrum [11], Mango [4], XPipes [3] and AEthereal [7]. While a lot of research has been done, to our knowledge there has not been many demonstrations of NoCs in real applications.…”

Section: Introductionmentioning

confidence: 99%

A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip

Stensgaard

Bjerregaard

Sparsø

et al. 2006

9th EUROMICRO Conference on Digital System Design (DSD'06)

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“…Specifically, the connection path between the source and destination pair of GS packets is built at the time before they are injected onto the network [44][45][46][47][48][49][50][51]. However, this kind of static preallocation may result in high service latency and does not consider hotspots created by temporal shifts in data requirements, thus, leads to a rather unscalable NoC.…”

Section: Connection-oriented Schemementioning

confidence: 99%

Networks on Chips: Structure and Design Methodologies

Tsai

Lan

et al. 2011

Journal of Electrical and Computer Engineering

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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for onchip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.

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A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

Abstract: On-chip networks for future system-on-chip

Cited by 226 publications

References 16 publications

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs

A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip

Networks on Chips: Structure and Design Methodologies

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