A room temperature 0.1 μm CMOS on SOI

Shahidi, G.; Anderson, Clint; Chappell, B.A.; Chappell, T.I.; Comfort, J.H.; Davari, B.; Dennard, R.H.; Franch, R.; McFarland, P.A.; Neely, J.S.; Ning, T.H.; Polcari, M.R.; Warnock, J.

doi:10.1109/16.337456

Cited by 79 publications

(12 citation statements)

References 14 publications

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“…Partially depleted SOI MOSFET's have been gaining interest thanks to a better threshold voltage control, an easier fabrication process and better scalability than fully depleted SOI MOSFET [1][2][3][4]. One of the main factors that limits the performance of these devices is the strong influence of the floating body effects.…”

Section: Introductionmentioning

confidence: 99%

Impact of Halo Implantation on the Lifetime Assessment in Partially Depleted SOI Transistors

Galeti¹,

Martino²,

Simoen³

et al. 2006

ECS Trans.

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This paper investigates the impact of the presence of a HALO implanted region on the lifetime analysis, based on a study of drain current switch-off transients. The latter were experimentally determined and compared with two-dimensional numerical simulations for PD SOI nMOSFET devices fabricated in a 0.13 µm CMOS technology. This study investigated for different channel lengths the drain current transient in relation with devices parameters such as the body potential, threshold voltage and the current density in the source/drain junctions.In the HALO devices the hole current density through the junctions between source/drain and body were not very significant, so that the influence of the junction is only due to the capacitive coupling between source/body and drain/body channel. For the channel length range studied (from 10 to 0.2µm), the transient time of HALO devices suffers from a 56% reduction. However, in the no HALO devices, there is beyond the capacitive coupling also a significant increase in the hole current density, causing a transient time reduction of 74%, for the same channel length range.

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Section: Introductionmentioning

confidence: 99%

Impact of Halo Implantation on the Lifetime Assessment in Partially Depleted SOI Transistors

Galeti¹,

Martino²,

Simoen³

et al. 2006

ECS Trans.

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“…The effect is observed as parasitics by some reports [3]- [4] but are seen as potential benefits to be taken advantage of by others [5]- [6]. When the body of PDSOI is floating, VBS varies during normal switching hence leading to threshold voltage variation and floating body effects such as kink behaviour and self heating [7]. To account for floating body effects, circuit design techniques must be modified; several types of body-contact architectures have been reported [8]- [9].…”

Section: Introductionmentioning

confidence: 89%

Effects of body contact on output characteristics of 0.5 micron MOSFET on thick bonded SOI substrate

Hanim

Sidek

Ahmad

2004

2004 IEEE International Conference on Semiconductor Electronics

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Effects of body contact on the output characteristics are investigated on 0.5 micron gate length MOSFET. The device employs bulk silicon CMOS technology that is fabricated on a 1.5 gm thick device layer of a Bonded Silicon-OnInsulator (BSOI) substrate. Body contact is achieved through the well contact underneath LOCOS above the buried oxide. Current-voltage measurements are carried out to characterize the output characteristics comparing with and without contact to the substrate. Results of partially-depleted SOI devices are compared to 0.5 micron MOSFET on bulk silicon wafer. Results show that floatingbody devices exhibit kink in the saturation region with earlier breakdown voltage. Applying body contact for 0.5 micron SOI device eliminates the kink and delays the breakdown voltage. Body-contacted SOI device in turn is found to exhibit negative resistance behaviour for higher gate voltages in the saturation region.

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“…A schematic cross section of CMOS on SO1 is shown in Fig. 13 [38]. The performance improvement of SO1 compared to bulk CMOS is mainly due to the reduction nFET pFET of parasitic capacitances and body effect.…”

Section: ) Interconnect Issues For High-per$ormance Applicationsmentioning

confidence: 99%

CMOS scaling for high performance and low power-the next ten years

1995

Self Cite

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A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described, one optimized for highest speed and the other trading offspeed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 pm channel length at 2.5 V down to sub-0.1 p m at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the powersupply voltage will lead to a substantial rise in standby power compared to active power, and some tradeoffs of performance andor changes in design methods must be made. Key technology elements and their impact on scaling are discussed.It is shown that a speed improvement of about 7x and over two orders of magnitude improvement in power-delay product (mW/MlPS) are expected by scaling of bulk CMOS down to the sub-0.1 pm regime as compared with today's high performance 0.6 p m devices at 5 V. However, the power density rises by a factor of 4 X for the high-speed scenario. The status of the siliconon-insulator (Sol) approach to scaled CMOS is also reviewed, showing the potential for about 3x savings in power compared to the bulk case at the same speed.

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A room temperature 0.1 μm CMOS on SOI

Cited by 79 publications

References 14 publications

Impact of Halo Implantation on the Lifetime Assessment in Partially Depleted SOI Transistors

Impact of Halo Implantation on the Lifetime Assessment in Partially Depleted SOI Transistors

Effects of body contact on output characteristics of 0.5 micron MOSFET on thick bonded SOI substrate

CMOS scaling for high performance and low power-the next ten years

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