A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography

Ghosh,; Alam,; Gupta, Puneet; Chowdhury,

doi:10.1109/dsd.2007.4341457

Cited by 15 publications

(16 citation statements)

References 5 publications

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“…That is k*P = P + P… + P, k times. Efficient and fast hardware PM's have already been achieved in several ways [6], [7], [8]. In [9], FPGA implementation of binary edwards curve using ternary representation over GF(2 m ) has been implemented.…”

Section: Introductionmentioning

confidence: 99%

Hardware realization of fast elliptic curve point multiplication using balanced ternary representation and pre-computation overGF(p)

Shylashree¹,

Sridhar²

2016

Journal of Discrete Mathematical Sciences and Cryptography

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Hardware realization of fast elliptic curve point multiplication using balanced ternary representation and pre-computation over Hardware realization of fast elliptic curve point multiplication using balanced ternary representation and pre-computation over GF(p) AbstractWe present a new hardware realization of fast elliptic curve Point Multiplication (PM) using the balanced ternary representation of the scalar multiplier. This hardware implementation uses multiple Elliptic Curve Point Tripler's (ECPT) and Elliptic Curve Point Adders (ECPA). Here, we pre-compute 3P, 9P, 27P, etc. using fast tripling and use them in calculating the final product over GF(p). However, to the best of our knowledge there exist no previous implementations of Balanced Ternary representation and pre-computation over GF(p) on FPGA platform. The FPGA synthesis results show that the proposed TPM6 and TPM24 methods can reach a speed up to 48.147 MHz and 50.814MHz; It needs 11.05µs and 49.45µs for the computation, consumes a power of 1.083W and 1.104W, occupies 2,657 and 5,449 *142 N. SHYLASHREE AND V. SRIDHAR slices respectively. The modular hardware approach used here provides high speed and scalability.

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Section: Introductionmentioning

confidence: 99%

Hardware realization of fast elliptic curve point multiplication using balanced ternary representation and pre-computation overGF(p)

Shylashree¹,

Sridhar²

2016

Journal of Discrete Mathematical Sciences and Cryptography

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“…Güneysu and Paar present in [13] a very fast approach based on special DSP FPGA slices, achieving processing times of 620 μs for a 256-bit scalar multiplication on a Virtex-4 FPGA. The implementation presented here is based on an F p ALU presented by Ghosh et al in [14]. Implementation approaches on CMOS standard cells can be found, for example, in [15,16] This contribution presents an FPGA-based autonomous ECDSA system for longer key lengths of 256 bit containing all necessary subsystems for application in embedded systems on reconfigurable hardware.…”

Section: Related Workmentioning

confidence: 99%

Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems

Glas

Sander

Stuckert

et al. 2011

International Journal of Reconfigurable Computing

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Growing ubiquity and safety relevance of embedded systems strengthen the need to protect their functionality against malicious attacks. Communication and system authentication by digital signature schemes is a major issue in securing such systems. This contribution presents a complete ECDSA signature processing system over prime fields for bit lengths of up to 256 on reconfigurable hardware. By using dedicated hardware implementation, the performance can be improved by up to two orders of magnitude compared to microcontroller implementations. The flexible system is tailored to serve as an autonomous subsystem providing authentication transparent for any application. Integration into a vehicle-to-vehicle communication system is shown as an application example.

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“…In order to using the same adder units shown in Figure 1, Binary Modular Inversion Algorithm presented in [23] is selected. By assigning a instead of 1 to variable s in step 1 of Algorithm 5 given bellow, the result y satisfies y = a/x.…”

Section: Modular Inversionmentioning

confidence: 99%

A Low Hardware Consumption Elliptic Curve Cryptographic Architecture over GF(p) in Embedded Application

Zheng

Zhang

et al. 2018

Electronics

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Abstract:In this paper, a low hardware consumption design of elliptic curve cryptography (ECC) over GF(p) in embedded applications is proposed. The adder-based architecture is explored to reduce the hardware consumption of performing scalar multiplication (SM). The Interleaved Modular Multiplication Algorithm and Binary Modular Inversion Algorithm are improved and implemented with two full-word adder units. The full-word register units for data storage are also optimized. The design is based on two full-word adder units and twelve full-word register units of pipeline structure and was implemented on Xilinx Virtex-4 platform. Design Compiler is used to synthesized the proposed architecture with 0.13 µm CMOS standard cell library. For 160, 192, 224, 256 field order, the proposed architecture consumes 5595, 7080, 8423, 9370 slices, respectively, and saves 17.58∼54.93% slice resources on FPGA platform when compared with other design architectures. The synthesized result uses 35.43 k, 43.37 k, 50.38 k, 57.05 k gate area and saves 52.56∼91.34% in terms of gate count in comparison. The design takes 2.56∼4.07 ms to perform SM operation over different field order under 150 MHz frequency. The proposed architecture is safe from simple power analysis (SPA). Thus, it is a good choice for embedded applications.

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A Robust GF(p) Parallel Arithmetic Unit for Public Key Cryptography

Cited by 15 publications

References 5 publications

Hardware realization of fast elliptic curve point multiplication using balanced ternary representation and pre-computation overGF(p)

Hardware realization of fast elliptic curve point multiplication using balanced ternary representation and pre-computation overGF(p)

Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems

A Low Hardware Consumption Elliptic Curve Cryptographic Architecture over GF(p) in Embedded Application

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