A robust dynamic voltage scaling scheme for FPGAs with IR drop compensation

Zhao, Shuze; Ahmed, Ibrahim; Khakpour, Armina; Betz, Vaughn; Trescases, Olivier

doi:10.1109/apec.2017.7931114

Cited by 7 publications

(3 citation statements)

References 14 publications

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“…The contribution of each individual component to the PDN's impedance is distinct at diferent frequencies. While in lower frequencies, the equivalent impedance of the PDN is dominated by the voltage regulator's characteristics, in higher frequencies, the of-chip and on-chip components are contributing most to the impedance [25,53,54].…”

Section: Power Distribution Network (Pdn) Characterizationmentioning

confidence: 99%

ScatterVerif: Verification of Electronic Boards Using Reflection Response of Power Distribution Network

Mosavirik

Ganji

Schaumont

et al. 2022

J. Emerg. Technol. Comput. Syst.

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The globalization of electronic systems’ fabrication has made some of our most critical systems vulnerable to supply chain attacks. Implanting spy chips on the printed circuit boards (PCBs) or replacing genuine components with counterfeit/recycled ones are examples of such attacks. Unfortunately, conventional attack detection schemes for PCBs are ad-hoc, costly, unscalable, and error-prone. This work introduces a holistic physical verification framework for PCBs, called ScatterVerif , based on the characterization of the PCBs’ power distribution network (PDN). First, we demonstrate how scattering parameters, frequently used for impedance characterization of RF circuits, can characterize the entire PCB with a single measurement. Second, we present how a class of machine learning algorithms, namely the Gaussian Mixture Model, can be applied to the measurements to automatically classify/cluster the genuine and tampered/counterfeit PCBs. We show that these attacks affect the overall impedance of a PCB differently in various frequency ranges , and hence, the conventional impedance measurements using a constant-frequency electrical stimulus might leave the attack undetected. We conduct extensive experiments on counterfeit and tampered devices and demonstrate that these attacks can be detected with a high-confidence. Finally, we show that the acquired data from the PDN characterization can also be deployed for fingerprinting genuine PCBs.

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Section: Power Distribution Network (Pdn) Characterizationmentioning

confidence: 99%

ScatterVerif: Verification of Electronic Boards Using Reflection Response of Power Distribution Network

Mosavirik

Ganji

Schaumont

et al. 2022

J. Emerg. Technol. Comput. Syst.

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“…The Intel Stratix 10 FPGA provides SmartVoltage ID control over VCC as its standard option that enables a smart voltage regulator to operate the device at lower VCC while maintaining performance [3]. Using these features, system level DVFS techniques are proposed for FPGAs [1,[4][5][6][7]. Hosseinabady et al [8] explain how to scale the voltage of the core logic in the Xilinx Zynq SoC.…”

Section: Preliminariesmentioning

confidence: 99%

“…They also calculate the timing overhead of scaling the voltage to shut down the FPGA core logic. A MicroBlaze-based light-weight soft-core IP is proposed by [4] to read and set the voltage lanes on the Zynq SoC through on-board voltage regulators supporting the PMBus protocol [9]. Using this IP, Nunez-Yanez et al [1] propose a dynamic voltage and frequency scaling technique on the Xilinx Zynq to reduce the energy consumption of the motion estimation task.…”

Section: Preliminariesmentioning

confidence: 99%

Dynamic Energy Management of FPGA Accelerators in Embedded Systems

Hosseinabady

Nunez-Yanez

2018

ACM Trans. Embed. Comput. Syst.

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In this paper, we investigate how to utilise an FPGA in an embedded system to save energy. For this purpose, we study the energy efficiency of a hybrid FPGA-CPU device that can switch task execution between hardware and software with focus on periodic tasks. To increase the applicability of this task switching, we also consider the voltage and frequency scaling (VFS) applied to the FPGA to reduce the system energy consumption. We show that in some cases, if the task's period is higher than a specific level, the FPGA accelerator cannot reduce the energy consumption associated to the task and the software version is the most energy efficient option. We have applied the proposed techniques to a robot map creation algorithm as a case study which shows up to 38% energy reduction compared to the FPGA implementation. Overall, experimental results show up to 48% energy reduction by applying the proposed techniques at runtime on thirteen individual tasks.

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