A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications

Giacomin, Edouard; Greenberg-Toledo, Tzofnat; Kvatinsky, Shahar; Gaillardon, Pierre-Emmanuel

doi:10.1109/tcsi.2018.2872455

Cited by 44 publications

(51 citation statements)

References 34 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The devised BDPE aims at improving the performance of binary convolution while reducing the number of data transfers by locally storing the most used kernels. Accordingly, the base block used in this work, proposed in [15], implements the binary dot product using the compute capabilities of RRAM, while also providing storage. The operands involved in the binary dot product are a constant binary kernel stored in the RRAM array in the form of resistance values and a binary vector supplied as an input.…”

Section: A Architecture Of the Binary Dot Product Enginementioning

confidence: 99%

“…The operands involved in the binary dot product are a constant binary kernel stored in the RRAM array in the form of resistance values and a binary vector supplied as an input. By selecting the appropriate kernel local address and applying the input data to the RRAM array, the XNOR phase of the convolution is performed as a memory readout using custom XNOR sense amplifiers [15]. Then, a fully-digital combinational circuit counts the number of logic ones to determine the result of the binary dot product operation.…”

Section: A Architecture Of the Binary Dot Product Enginementioning

confidence: 99%

“…Fig. 1b depicts the RRAM-based convolutional block used in this work inspired by [15]. performing the XNOR of two inputs as an alternative to using the primary RRAM-based XNOR mechanism.…”

Section: A Architecture Of the Binary Dot Product Enginementioning

confidence: 99%

“…Thus, whenever the kernels are stored in the unit, there is no need for transferring them from memory, reducing the overall memory accesses. Since Resistive Random-Access Memories (RRAMs) excel by their ability of enabling in-memory computing capabilities while providing storage support [14], the novel BDPE uses a robust and energy efficient RRAM-based convolutional block based on [15]. Contrarily to previous analog proposals (e.g., [16]) whose accuracy can be severely degraded due to process variation, this block operates in the digital domain.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

Vieira

Giacomin

Qureshi

et al. 2019

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)

Self Cite

View full text Add to dashboard Cite

The need for running complex Machine Learning (ML) algorithms, such as Convolutional Neural Networks (CNNs), in edge devices, which are highly constrained in terms of computing power and energy, makes it important to execute such applications efficiently. The situation has led to the popularization of Binary Neural Networks (BNNs), which significantly reduce execution time and memory requirements by representing the weights (and possibly the data being operated) using only one bit. Because approximately 90% of the operations executed by CNNs and BNNs are convolutions, a significant part of the memory transfers consists of fetching the convolutional kernels. Such kernels are usually small (e.g., 3×3 operands), and particularly in BNNs redundancy is expected. Therefore, equal kernels can be mapped to the same memory addresses, requiring significantly less memory to store them. In this context, this paper presents a custom Binary Dot Product Engine (BDPE) for BNNs that exploits the features of Resistive Random-Access Memories (RRAMs). This new engine allows accelerating the execution of the inference phase of BNNs. The novel BDPE locally stores the most used binary weights and performs binary convolution using computing capabilities enabled by the RRAMs. The system-level gem5 architectural simulator was used together with a C-based ML framework to evaluate the system's performance and obtain power results. Results show that this novel BDPE improves performance by 11.3%, energy efficiency by 7.4% and reduces the number of memory accesses by 10.7% at a cost of less than 0.3% additional die area, when integrated with a 28 nm Fully Depleted Silicon On Insulator ARMv8 in-order core, in comparison to a fully-optimized baseline of YoloV3 XNOR-Net running in a unmodified Central Processing Unit.

show abstract

Section: A Architecture Of the Binary Dot Product Enginementioning

confidence: 99%

Section: A Architecture Of the Binary Dot Product Enginementioning

confidence: 99%

“…Fig. 1b depicts the RRAM-based convolutional block used in this work inspired by [15]. performing the XNOR of two inputs as an alternative to using the primary RRAM-based XNOR mechanism.…”

Section: A Architecture Of the Binary Dot Product Enginementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

Vieira

Giacomin

Qureshi

et al. 2019

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)

Self Cite

View full text Add to dashboard Cite

show abstract

“…These models can nevertheless achieve state-of-the-art performance on image recognition, while being multiplierless, and relying only on simple binary logic functions. First hardware implementations have already been investigated and have shown highly promising results [2], [6], [15], [16].…”

Section: Introductionmentioning

confidence: 99%

Stochastic Computing for Hardware Implementation of Binarized Neural Networks

et al. 2019

View full text Add to dashboard Cite

Binarized Neural Networks, a recently discovered class of neural networks with minimal memory requirements and no reliance on multiplication, are a fantastic opportunity for the realization of compact and energy efficient inference hardware. However, such neural networks are generally not entirely binarized: their first layer remains with fixed point input. In this work, we propose a stochastic computing version of Binarized Neural Networks, where the input is also binarized. Simulations on the example of the Fashion-MNIST and CIFAR-10 datasets show that such networks can approach the performance of conventional Binarized Neural Networks. We evidence that the training procedure should be adapted for use with stochastic computing. Finally, the ASIC implementation of our scheme is investigated, in a system that closely associates logic and memory, implemented by Spin Torque Magnetoresistive Random Access Memory. This analysis shows that the stochastic computing approach can allow considerable savings with regards to conventional Binarized Neural networks in terms of area (62% area reduction on the Fashion-MNIST task). It can also allow important savings in terms of energy consumption, if we accept reasonable reduction of accuracy: for example a factor 2.1 can be saved, with the cost of 1.4% in Fashion-MNIST test accuracy. These results highlight the high potential of Binarized Neural Networks for hardware implementation, and that adapting them to hardware constrains can provide important benefits.

show abstract

Reliability Improvement and Effective Switching Layer Model of Thin‐Film MoS₂ Memristors

Huang

Mohan

et al. 2023

Adv Funct Materials

View full text Add to dashboard Cite

Abstract2D memristors have demonstrated attractive resistive switching characteristics recently but also suffer from the reliability issue, which limits practical applications. Previous efforts on 2D memristors have primarily focused on exploring new material systems, while damage from the metallization step remains a practical concern for the reliability of 2D memristors. Here, the impact of metallization conditions and the thickness of MoS2 films on the reliability and other device metrics of MoS2‐based memristors is carefully studied. The statistical electrical measurements show that the reliability can be improved to 92% for yield and improved by ≈16× for average DC cycling endurance in the devices by reducing the top electrode (TE) deposition rate and increasing the thickness of MoS2 films. Intriguing convergence of switching voltages and resistance ratio is revealed by the statistical analysis of experimental switching cycles. An “effective switching layer” model compatible with both monolayer and few‐layer MoS2, is proposed to understand the reliability improvement related to the optimization of fabrication configuration and the convergence of switching metrics. The Monte Carlo simulations help illustrate the underlying physics of endurance failure associated with cluster formation and provide additional insight into endurance improvement with device fabrication optimization.

show abstract

A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications

Cited by 44 publications

References 34 publications

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

Stochastic Computing for Hardware Implementation of Binarized Neural Networks

Reliability Improvement and Effective Switching Layer Model of Thin‐Film MoS₂ Memristors

Contact Info

Product

Resources

About

A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications

Cited by 44 publications

References 34 publications

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

Stochastic Computing for Hardware Implementation of Binarized Neural Networks

Reliability Improvement and Effective Switching Layer Model of Thin‐Film MoS2 Memristors

Contact Info

Product

Resources

About

Reliability Improvement and Effective Switching Layer Model of Thin‐Film MoS₂ Memristors