A Robust and Fast Digital Background Calibration Technique for Pipelined ADCs

Fan, Jen-Lin; Wang, Chung-Yi; Wu, Jieh-Tsorng

doi:10.1109/tcsi.2007.895231

Cited by 29 publications

(18 citation statements)

References 10 publications

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“…The speed calculates by data samples per stage V. CONCLUSION The proposed algorithm can calibrate capacitor mismatch error, finite amplifier gain error and amplifier nonlinearity of pipelined ADC in background. The convergence time for each stage is about 2 samples, which is more than 200 times faster than [4] with the same ADC topological structure. Both 1.5-bit per stage and multi-bit per stage are supported, just need to redefine the reference voltage.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…This can result in a low signal-to-dither ratio or even let the LMS procedure not converge. To solve this problem, split ADC is proposed in [1] and [4].…”

Section: A Radix Extractionmentioning

confidence: 99%

“…The two split ADC share the same input signal but with opposite polarity. And [4] utilize a split ADC and the split channel has the same input as the normal channel, cost function of the split ADC's is different from [1]. [5] introduced another method to decrease the signal-to-dither ratio by selectively using dithers of different magnitudes depending on the input signal level, and it has a convergence time of 2 samples per stage measured with 15-bit accuracy.…”

Section: Introductionmentioning

confidence: 99%

“…In this work, we extend the technique of [1] to fits pipelined ADCs, a digital calibration switch array control unit is proposed, simulation result shows a convergence time about 2 samples, which is more than 200 times faster compared to [4] with the same ADC topological structure.…”

Section: Introductionmentioning

confidence: 99%

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A fast correlation based background digital calibration for pipelined ADCs

Yan

2012

2012 IEEE Asia Pacific Conference on Circuits and Systems

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This paper presents a fast background digital calibration method for pipelined analog-to-digital converters (ADCs) that is robust and converges fast. To avoid the problem of input signal amplitude limitation, the proposed calibration technique takes advantage of the digital redundancy architecture by injecting pseudo-random noise (PN) in the sub-ADC. A split ADC architecture combined with a switch array control unit is also proposed to minimize the correlation between the input signal and the injecting PN signal. Simulation result shows, when the capacitor error is 0.1%, and the gain error between the two channel is 1%, the calibration time is about samples simulated with 15-bit accuracy with a 0.32/-0.33 LSB DNL and a 0.50/-0.24 LSB INL, and the SNDR is 91.5 dB, the SFDR is 110.3 dB.Index Terms-Analog-to-digital converter, digital background calibration, pipelined ADC.

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Section: Simulation Resultsmentioning

confidence: 99%

“…This can result in a low signal-to-dither ratio or even let the LMS procedure not converge. To solve this problem, split ADC is proposed in [1] and [4].…”

Section: A Radix Extractionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A fast correlation based background digital calibration for pipelined ADCs

Yan

2012

2012 IEEE Asia Pacific Conference on Circuits and Systems

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“…We 978-1-4244-5271-2/10/$26.00 ©2010 IEEE found the split-capacitor correlation-based background calibration algorithm is quite robust that the whole algorithm is not dependent on the input signal distribution to correct the linear and the nonlinear errors [3]. The extracted errors can be easily calculated from the transition heights of the transfer curves of the 1.5-bit MDAC.…”

Section: Fig 2 Pipeline Adc Architecturementioning

confidence: 98%

Digitally-assisted analog designs for submicron CMOS technology

Lai

Lin

Weng

et al. 2010

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test

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Three different digitally-assisted analog designs are presented to demonstrate the powerful way to solve the analog design deficiencies in the submicron CMOS technology. A 200 MS/s 12-bit pipeline ADC is using the split-capacitor correlation method to solve the linear and nonlinear problems. A 1 GS/s 14-bit current-steering DAC is using the programmable sub-DAC to continuously trimming the current mismatches. A 25 MS/s 16-bit 6 6' ADC is using the adaptive way to correct the leakage noise and DAC nonlinearity.

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