A RISC-V Based Medical Implantable SoC for High Voltage and Current Tissue Stimulus

Arnaud, Alfredo; Miguez, Matías; Gak, Joel; Puyol, Rafael; García-Ramírez, Ronny; Solera-Bolanos, E.; Castro-González, Reinaldo; Molina-Robles, Roberto; Chacón-Rodríguez, Alfonso; Rimolo-Donadío, Renato

doi:10.1109/lascas45839.2020.9068969

Cited by 7 publications

(1 citation statement)

References 16 publications

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“…The RISC-V architecture is being implemented for several health monitoring devices. A recent study by [29,30] presents a cutting-edge technology in form of an implantable medical device (IMD) for conditioning the human body electrical activity which runs on a RISC-V processor. [11] also produced a RISC-V-based microprocessor that could be used in devices for personalized health management aside from other devices like electronic voting machines, smart cards, etc.…”

Section: A Results and Discussionmentioning

confidence: 99%

Watchdog Monitoring for Detecting and Handling of Control Flow Hijack on RISC-V-based Binaries

Oyinloye¹,

Speakman²,

Eze³

et al. 2022

IJACSA

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Control flow hijacking has been a major challenge in software security. Several means of protections have been developed but insecurities persist. This is because existing protections have sometimes been circumvented while some resilient protections do not cover all applications. Studies have revealed that a holistic way of tackling software insecurity could involve watchdog monitoring and detection via Control Flow Integrity (CFI). The CFI concept has shown a good measure of reliability to mitigate control flow hijacking. However, sophisticated attack techniques in the form of Return Oriented Programming (ROP) have persisted. A flexible protection is desirable, which not only covers as many architecture structures as possible but also mitigates known resilient attacks like ROP. The solution proffered here is a hybrid of CFI and watchdog timing via inter-process signaling (IP-CFI). It is a software-based protection that involves recompilation of the target program. The implementation here is on vulnerable RISC-V-based process but is flexible and could be adapted on other architectures. We present a proof of concept in IP-CFI which when applied to a vulnerable program, ROP is mitigated. The target program incurs a run-time overhead of 1.5%. The code is available.

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Section: A Results and Discussionmentioning

confidence: 99%