A Review on Non-Conventional Analog Circuit Design Techniques for Low Voltage Low Power Operation

Abstract

Designing of integrated circuits under low voltage low power condition is becoming an indispensible issue in today's era. Reducing the power consumption and power supply voltage is the key challenge as it makes certain about reliability of device, averts overheating of the circuits and extends the battery for portable electronics, battery powered implantable and wearable medical devices. Small size and light weight devices are in demand in modern span. Various innovative techniques and methods have been suggested and implemented in literature to decrease the power consumption and enhance the speed by changing the base material of the chips from traditional Silicon to III-V material like Gallium Arsenide. Non-conventional techniques have played pivoted role in minimizing the design complexity and drive the power supply voltage towards the threshold voltage of MOS transistors. This paper presents the operation principle, advantages and disadvantages of non-conventional analog circuit design techniques such as Bulk driven technique, Floating gate technique and Quasi Floating gate technique, thus enabling circuit designers to select the proper design technique based on application requirements.

Variability aware ultra-low power design of NOR/NAND gate using non-conventional techniques

“…The non-conventional techniques such as FGMOS, Quasi-FGMOS (QFGMOS) and bulk-driven MOS technology are designed to operate under low power low voltage conditions along with the optimized performance [14]. The adoption of emerging technology like CNTFET has also been employed to minimize device size without sacrificing performance.…”

“…FGMOS technology has two main features: threshold control and multiple inputs [14]. The fact that FGMOS has several inputs makes it a good candidate for use as an active building component in designing of digital logic gates [14]. Figure 1 shows a schematic representation of a multiple input n-type FGMOS.…”

“…The most effective way of reducing power dissipation is to lower the threshold and power supply voltages. Another alternate solution in term of nonconventional design methods such as Level shifters, sub-threshold MOSFETs, bulk-driven MOSFETs, and floating gate MOSFETs have reported in the literature [12][13][14]27]. Out of these, FGMOS has the distinct benefit of tunability of the threshold voltage, which may be reduced from its traditional value, making it appropriate for low voltage low power applications.…”

“…Out of these, FGMOS has the distinct benefit of tunability of the threshold voltage, which may be reduced from its traditional value, making it appropriate for low voltage low power applications. FGMOS technology has two main features: threshold control and multiple inputs [14]. The fact that FGMOS has several inputs makes it a good candidate for use as an active building component in designing of digital logic gates [14].…”

16-Bit multiplier optimization based on Wallace tree and Booth algorithm

“…Multiplier is an important arithmetic unit commonly used in computers, and its performance and power consumption have a significant impact on the overall performance and power consumption of computer systems [1]. Therefore, the optimization of the multiplier has always been one of the hot research topics in the field of computer architecture [2].…”