“…Several excellent surveys have been devoted to designs, categorizations, and protections for HT problems [1], [4], [7], [8], [13]- [17], [21], [35]- [39]. For example, Sumathi et al provided a comprehensive review of complex HT threats and illustrated feasible countermeasures against HT attacks for PLD and ASIC life cycles [1]. Zhang et al highlighted the potential security and trust threats associated with FPGA-based systems from a market perspective and discussed the relevant solutions available for each party [15].…”
Section: B Motivation and Contributionsmentioning
confidence: 99%
“…The tremendous advancements in semiconductor technology have resulted in a large number of participants coordinating during the design and manufacturing process of integrated circuits (ICs) [1], [2]. Particularly given the continuously increasing complexity of ICs, increasingly greater numbers of specialized teams and/or companies, typically dispersed geographically, are involved in this complex process to increase efficiency and manufacturability.…”
The remarkable success of machine learning (ML) in a variety of research domains has inspired academic and industrial communities to explore its potential to address hardware Trojan (HT) attacks. While numerous works have been published over the past decade, few survey papers, to the best of our knowledge, have systematically reviewed the achievements and analyzed the remaining challenges in this area. To fill this gap, this article surveys ML-based approaches against HT attacks available in the literature. In particular, we first provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture. Based on the review, we further discuss the lessons learned in and challenges arising from previous studies. Despite current work focusing more on chip-layer HT problems, it is notable that novel HT threats are constantly emerging and have evolved beyond chips and to the component, device, and even behavior layers, therein compromising the security and trustworthiness of the overall hardware ecosystem. Therefore, we divide the HT threats into four layers and propose a hardware Trojan defense (HTD) reference model from the perspective of the overall hardware ecosystem, therein categorizing the security threats and requirements in each layer to provide a guideline for future research in this direction.
“…Several excellent surveys have been devoted to designs, categorizations, and protections for HT problems [1], [4], [7], [8], [13]- [17], [21], [35]- [39]. For example, Sumathi et al provided a comprehensive review of complex HT threats and illustrated feasible countermeasures against HT attacks for PLD and ASIC life cycles [1]. Zhang et al highlighted the potential security and trust threats associated with FPGA-based systems from a market perspective and discussed the relevant solutions available for each party [15].…”
Section: B Motivation and Contributionsmentioning
confidence: 99%
“…The tremendous advancements in semiconductor technology have resulted in a large number of participants coordinating during the design and manufacturing process of integrated circuits (ICs) [1], [2]. Particularly given the continuously increasing complexity of ICs, increasingly greater numbers of specialized teams and/or companies, typically dispersed geographically, are involved in this complex process to increase efficiency and manufacturability.…”
The remarkable success of machine learning (ML) in a variety of research domains has inspired academic and industrial communities to explore its potential to address hardware Trojan (HT) attacks. While numerous works have been published over the past decade, few survey papers, to the best of our knowledge, have systematically reviewed the achievements and analyzed the remaining challenges in this area. To fill this gap, this article surveys ML-based approaches against HT attacks available in the literature. In particular, we first provide a classification of all possible HT attacks and then review recent developments from four perspectives, i.e., HT detection, design-for-security (DFS), bus security, and secure architecture. Based on the review, we further discuss the lessons learned in and challenges arising from previous studies. Despite current work focusing more on chip-layer HT problems, it is notable that novel HT threats are constantly emerging and have evolved beyond chips and to the component, device, and even behavior layers, therein compromising the security and trustworthiness of the overall hardware ecosystem. Therefore, we divide the HT threats into four layers and propose a hardware Trojan defense (HTD) reference model from the perspective of the overall hardware ecosystem, therein categorizing the security threats and requirements in each layer to provide a guideline for future research in this direction.
“…Unfortunately, like software, the hardware still can not be trusted. The risks of the chips should At present, the hidden risk of the integrated circuit mainly comes from the malicious circuits implanted inside which are called Hardware Trojan (HT in short) [3]. In recent years, there are some reports like the following, the defense science council reported in March 2017 that U.S. military weapons systems might have been injected with HTs [4].…”
With the booming development of the cyber-physical system, human society is much more dependent on information technology. Unfortunately, like software, hardware is not trusted at all, due to so many third parties involved in the separated integrated circuit's (IC) design and manufacturing stages for the high profit. The malicious circuits (named Hardware Trojans) can be implanted during any stage of the ICs' design and manufacturing process. However, the existing pre-silicon approaches based on machine learning theory have good performance, they all belong to supervised learning methods, which have a key prerequisite that is numerous already known information. Meanwhile, hardware Trojans are even more unimaginable because today's ICs are becoming more complicated. The known information is even harder to gain. Furthermore, the training process for supervised learning methods tends to be time-consuming and generally requires a huge amount of balanced training data. Therefore, this paper proposes an unsupervised hardware Trojans detection approach by combined the principal component analysis (PCA) and local outlier factor (LOF) algorithm, called PL-HTD. We firstly visualize the distribution features of normal nets and Trojan nets, and then reveal the differences between the two types of nets to reduce the dimension of the feature set. According to the outliers of each net, the abnormal nets are selected and verified by professionals later to confirm whether it is a true Trojan relative to the host circuit to realize the detection. The experiments show that the proposed method can detect hardware Trojans effectively and reduce the cost of manual secondary detection. For the Trust-HUB benchmarks, the PL-HTD achieves up to 73.08% TPR and 97.52% average TNR, moreover, it achieves average 96.00% accuracy, which shows the feasibility and efficiency of hardware Trojans detecting by employing a method without the guidance of class label information. INDEX TERMS hardware security, hardware Trojan detection, integrated circuit, unsupervised machine learning, LOF
“…Obviously, this offshore foundries technology brings high-security risks to the entire electronics manufacturing industry. As the scale of ICs grows rapidly and manufacture mode becomes more flexible, the main security issues of ICs are caused by the implant of the malicious circuits, named Hardware Trojans (HTs) [ 1 ]. The development trend of the ICs results in them extremely vulnerable to attack by HTs [ 2 ].…”
Section: Introductionmentioning
confidence: 99%
“…Moreover, the detailed discussion of HTs safety on RF IC and AMS circuits is not included in this article. Sumathi et al [ 1 ] studied the attack and defense of HTs on programmable logic devices (PLD) and application specific ICs (ASIC). Nonetheless, the characteristics of HTs have not been classified.…”
Diverse and wide-range applications of integrated circuits (ICs) and the development of Cyber Physical System (CPS), more and more third-party manufacturers are involved in the manufacturing of ICs. Unfortunately, like software, hardware can also be subjected to malicious attacks. Untrusted outsourced manufacturing tools and intellectual property (IP) cores may bring enormous risks from highly integrated. Attributed to this manufacturing model, the malicious circuits (known as Hardware Trojans, HTs) can be implanted during the most designing and manufacturing stages of the ICs, causing a change of functionality, leakage of information, even a denial of services (DoS), and so on. In this paper, a survey of HTs is presented, which shows the threatens of chips, and the state-of-the-art preventing and detecting techniques. Starting from the introduction of HT structures, the recent researches in the academic community about HTs is compiled and comprehensive classification of HTs is proposed. The state-of-the-art HT protection techniques with their advantages and disadvantages are further analyzed. Finally, the development trends in hardware security are highlighted.
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