A review of the top of the barrier nanotransistor models for semiconductor nanomaterials

Chuan, Mu Wen; Wong, Kien Liong; Hamzah, Afiq; Rusli, Shahrizal; Alias, Nurul Ezaila; Lim, Cheng Siong; Tan, Michael Loong Peng

doi:10.1016/j.spmi.2020.106429

Cited by 13 publications

(6 citation statements)

References 94 publications

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“…f L and f R are the Fermi-Dirac distribution functions of the transversal energy E t and longitudinal energy E s at the left and right reservoirs, respectively. For 1D DOS based on carbon nanotubes and Si nanowires, the tunneling current can be expressed as an integral over the longitudinal energy E s [7,24,25]. By an extension of the formulation of (1), the model for p-channel Ge nanowire is modified to take into account phonon and surface roughness scattering in the channel and SD tunneling [25,26].…”

Section: Tunneling Current Modelmentioning

confidence: 99%

“…For 1D DOS based on carbon nanotubes and Si nanowires, the tunneling current can be expressed as an integral over the longitudinal energy E s [7,24,25]. By an extension of the formulation of (1), the model for p-channel Ge nanowire is modified to take into account phonon and surface roughness scattering in the channel and SD tunneling [25,26]. T α (E) is the tunneling probability of the energy barrier between source and drain (α = sd) or between channel and gate (α = cg).…”

Section: Tunneling Current Modelmentioning

confidence: 99%

“…In the sequential tunneling (ST) model, the interaction of carriers results in other tunneling events due to fluctuations in the potential [16,21,28,29]. In the case of stress-induced leakage currents (SILCs) through the gate oxide, the noise properties are explained by trap-assisted tunneling, a two-step process in which electrons first tunnel from the channel to a trap in the oxide, then from the trap to the gate [12,[21][22][23][24][25][26][27][28][29][30]. Analogously, by introducing a two-step tunneling process for the single barrier in both the sourcedrain and channel-gate direction, we can define four different flow rates, namely, the generation flow rate injected from the left or right (F + L or F − R ) and the recombination flow rate transmitted to the left or right (F − L or F + R ), as shown in Figure 1a,b [31][32][33].…”

Section: Shot Noise Modelmentioning

confidence: 99%

See 2 more Smart Citations

Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs

Lee

2021

Nanomaterials

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A single unified analytical model is presented to predict the shot noise for both the source-to-drain (SD) and the gate tunneling current in sub-10 nm MOSFETs with ultrathin oxide. Based on the Landauer formula, the model is constructed from the sequential tunneling flows associated with number fluctuations. This approach provides the analytical formulation of the shot noise as a function of the applied voltages. The model performs well in predicting the Fano factor for shot noise in the SD and gate tunneling currents.

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Section: Tunneling Current Modelmentioning

confidence: 99%

Section: Tunneling Current Modelmentioning

confidence: 99%

Section: Shot Noise Modelmentioning

confidence: 99%

See 1 more Smart Citation

Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs

Lee

2021

Nanomaterials

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“…With the obtained electronic properties, the work then proceeds with device-level modelling by employing the top-of-the-barrier (TOB) ballistic nanotransistor model [ 36 ], which has been widely used to predict the performance limits of various low-dimensional materials [ 37 ]. In this work, a double-gated FET structure with L g = 10 nm is employed, where the gate oxide layers are SiO 2 ( ε r = 3.9) with thickness of t OX = 1.5 nm .…”

Section: Modelling Proceduresmentioning

confidence: 99%

Semi-analytical modelling and evaluation of uniformly doped silicene nanotransistors for digital logic gates

et al. 2021

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Silicene has attracted remarkable attention in the semiconductor research community due to its silicon (Si) nature. It is predicted as one of the most promising candidates for the next generation nanoelectronic devices. In this paper, an efficient non-iterative technique is employed to create the SPICE models for p-type and n-type uniformly doped silicene field-effect transistors (FETs). The current-voltage characteristics show that the proposed silicene FET models exhibit high on-to-off current ratio under ballistic transport. In order to obtain practical digital logic timing diagrams, a parasitic load capacitance, which is dependent on the interconnect length, is attached at the output terminal of the logic circuits. Furthermore, the key circuit performance metrics, including the propagation delay, average power, power-delay product and energy-delay product of the proposed silicene-based logic gates are extracted and benchmarked with published results. The effects of the interconnect length to the propagation delay and average power are also investigated. The results of this work further envisage the uniformly doped silicene as a promising candidate for future nanoelectronic applications.

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“…According to Moore's law, the number of transistors in an integrated circuit would be doubled every 2 years [1]. However, the scaling of silicon (Si) complementary metal-oxide-semiconductor (CMOS) technology is expected to face its fundamental limit as it enters the sub-10 nm scaling regime [2,3]. To leverage these shortcomings, various innovations involving feld-efect transistors (FETs), such as the tunnelling FETs (TFETs) [4], nanowire FETs (NWFETs) [5], multibridge-channel FETs (MBCFETs) [6], and two-dimensional (2D) FETs, have been actively developed and studied.…”

Section: Introductionmentioning

confidence: 99%

Device Performance of Double-Gate Schottky-Barrier Graphene Nanoribbon Field-Effect Transistors with Physical Scaling

Chuan

Misnon

Alias

et al. 2023

Journal of Nanotechnology

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Moore’s law is approaching its limit due to various challenges, especially the size limit of the transistors. The International Roadmap for Devices and Systems (IRDS), the successor of International Technology Roadmap for Semiconductors (ITRS), has included 2D materials as an alternative approach for the More-than-Moore nanoelectronic applications. Among the 2D materials, graphene nanoribbons (GNRs) have been widely used as the alternative channel materials of field-effect transistors (FETs). In this paper, the impacts of physical scaling on the device performance of double-gate Schottky-barrier GNR FETs (DG-SB-GNRFETs) are investigated by using NanoTCAD ViDES simulation tool based on the tight-binding Hamiltonian and self-consistent solutions of 3D Poisson and Schrödinger equations with open boundary conditions within the nonequilibrium Green’s function formalism. The extracted device performance parameters include the subthreshold swing and on-to-off current ratio. The results suggest that the performances of DG-SB-GNRFETs are strongly dependent on their physical parameters, especially the widths of the GNRs.

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A review of the top of the barrier nanotransistor models for semiconductor nanomaterials

Cited by 13 publications

References 94 publications

Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs

Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs

Semi-analytical modelling and evaluation of uniformly doped silicene nanotransistors for digital logic gates

Device Performance of Double-Gate Schottky-Barrier Graphene Nanoribbon Field-Effect Transistors with Physical Scaling

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