A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC

Yip, Marcus; Chandrakasan, Anantha P.

doi:10.1109/isscc.2011.5746277

Cited by 69 publications

(26 citation statements)

References 3 publications

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“…For an N-bit SAR ADC it usually takes at least N clock cycles to complete one conversion. Since there is only one comparator and no other active components in the converter, SAR ADCs are highly power-efficient [11][12][13]. Moreover, owing to its dynamic nature, SAR ADCs are also amenable to technology scaling [14].…”

Section: Review Of Power-efficient Adc Architecturesmentioning

confidence: 99%

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Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Zhang

2014

Linköping Studies in Science and Technology. Dissertations

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Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters(ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successive-approximation-register (SAR) ADC exhibits significantly high energy efficiency due to its good trade-offs among power consumption, conversion accuracy, and design complexity. This thesis examines the physical limitations and investigates the design methodologies and circuit techniques for low-speed and ultra-low-power SAR ADCs.The power consumption of SAR ADC is analyzed and its lower bounds are formulated in the thesis. At low resolutions, power is bounded by minimum feature sizes; while at medium to high resolutions, power is bounded by thermal noise and capacitor mismatch. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity for high resolution, a bottom-up weight calibration technique is further proposed. It utilizes redundancy generated by a non-binary-weighted capacitive network, and measures the actual weights of more significant capacitors using less significant capacitors.Three SAR ADCs have been implemented. The first ADC, fabricated in a 0.13µm CMOS process, achieves 9.1ENOB with 53-nW power consumption at 1kS/s. The main key to achieve the ultra-low-power operation turns out to be the maximal simplicity in the ADC architecture and low transistor count. In addition, a dual-supply voltage scheme allows the SAR digital logic to operate at 0.4V, reducing the overall power consumption of the ADC by 15% without any loss in performance. Based on the understanding from the first ADC and motivated by the predicted power bounds, the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process has been further fabricated. It achieves a substantial (94%) improvement in power consumption with 3-nW total power at 1kS/s and 0.7V. Following the same concept of imposing maximal simplicity in the ADC architecture and taking advantage of the smaller feature size, the ultra-low-power consumption is achieved by a matched splitiv array capacitive DAC, a bottom-plate full-range input-sampling scheme, a latch-based SAR control logic, and a multi-V T design approach. The third ADC fabricated in 65nm CMOS process targets at a higher resolution of 14b and a wider bandwidth of 5KHz. It achieves 12.5ENOB with 1.98-µW power consumption at 0.8V and 10kS/s. To achieve the high resolution, the ADC implements a uniform-geometry non-binaryweighted capacitive DAC and employs a secondary-bit approach to dynamically shift decision levels for error correction. Moreover, a comparator with bias control utilizes the redundancy to reduce the power consumption....

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Section: Review Of Power-efficient Adc Architecturesmentioning

confidence: 99%

“…Two common approaches to performing the comparison are a latch proceeded by preamplifiers [18,21] or a single dynamic latch [12,22].…”

Section: Comparatormentioning

confidence: 99%

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Zhang

2014

Linköping Studies in Science and Technology. Dissertations

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“…However, applications such as sensor networks often have varying bandwidth and dynamic range requirements, making reconfigurable ADCs highly desirable. An example of a reconfigurable 5-to-10b SAR ADC whose power scales with resolution and sampling rate can be found in [50]. A resolution-reconfigurable DAC whose power scales exponentially with resolution is used to reduce CV 2 switching energy.…”

Section: A Reconfigurable Voltage-scalable Sar Adcmentioning

confidence: 99%

“…Voltage scaling, however, places a limit on the maximum f S , resulting in increased leakage energy per conversion. To address this, the ADC in [50] is duty cycled so that leakage powergating with a high-V T device can be used during the SLEEP state to further reduce power. These techniques allow the ADC to remain energy-efficient over a wide range of resolutions and sample rates.…”

Section: A Reconfigurable Voltage-scalable Sar Adcmentioning

confidence: 99%

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

Sinangil

Yip

Qazi

et al. 2012

IEEE Trans. Circuits Syst. II

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“…A previous implementation [3] achieves very low energy (150fJ/convstep), while still requiring a low jitter clock, digital postcorrection, and large area (0.02mm 2 ; 10× area with ideal scaling versus the proposed design). Other designs [4,5] implement low energy, resolution scalable SARs that require high accuracy current sources and low jitter timing references, both of which are not feasible in millimeter-scale wireless sensing applications. Additionally, these SAR-based ADCs require ~100× larger area (ideal scaling) than the proposed approach.…”

Section: Introductionmentioning

confidence: 99%

A 346μm<sup>2</sup> reference-free sensor interface for highly constrained microsystems in 28nm CMOS

Freyman

Fick

Blaauw

et al. 2013

2013 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A 346μm 2 reference-free, asynchronous VCO-based sensor interface circuit is demonstrated in 28nm LP CMOS. This design does not require high accuracy current sources, voltage sources, or low jitter timing references. It achieves wide resolution and voltage scalability, and consumes only ~1/100 th the area of prior approaches. Resolution can be scaled from 2.8 to 11.7 bits and V DD from 500mV to 1.0V.

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A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC

Cited by 69 publications

References 3 publications

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

A 346μm<sup>2</sup> reference-free sensor interface for highly constrained microsystems in 28nm CMOS

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A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC

Cited by 69 publications

References 3 publications

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

A 346&#x03BC;m<sup>2</sup> reference-free sensor interface for highly constrained microsystems in 28nm CMOS

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A 346μm<sup>2</sup> reference-free sensor interface for highly constrained microsystems in 28nm CMOS