A ReRAM-based non-volatile flip-flop with sub-V<inf>T</inf> read and CMOS voltage-compatible write

Abstract

Abstract-The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and program state, respectively. On the one hand, supply voltage scaling down to the near-threshold (near-VT) or even to the sub-threshold (sub-VT) domain is a commonly used, efficient technique to reduce both leakage power and active energy dissipation. On the other hand, emerging CMOS-compatible device technologies such as Resistive Memories (ReRAMs) enable non-volatile, on-chip data storage and zero-leakage sleep periods. For the first time, we present a ReRAM-based non-volatile flipflop which is optimized for sub-VT operation. Writing to the ReRAM devices works with a CMOS-compatible supply voltage. Thanks to near-VT and sub-VT operation and as compared to the write energy, which depends on the ReRAM technology, the read consumes only 5.4% of the total read+write energy. Monte Carlo simulations accounting for parametric variations in both the MOS transistors and the ReRAM devices confirm reliable data restore operation from the ReRAM devices at a sub-VT voltage as low as 400 mV, and a standard deviation of up to 5% of the nominal value of the ReRAM resistance.

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

“…This article extends our previous work [12] by introducing two new NVFF topologies and by presenting a detailed comparative analysis of all topologies.…”

“…Several architectural alternatives for the distribution of the high supply voltage are discussed in [12]. Here, we adopt the approach of dynamically rising the supply voltage of all NVFFs during a write operation, as shown in Fig.…”

Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology

“…Previous low power MFFs are designed by cascading two complementary latches [2][3][4][5]. In order to enhance MFF latency and reliability, we propose a modified MFF architecture with sense amplifier based flip-flop (SAFF) [20] [21].…”

“…Non-volatile MRAM has been implemented with different supply voltages (V dd is from 0.4 V to 2 V) [2][3][4][5]. Ultra thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology has been proposed and validated in low power circuit design [6].…”

Temporal memoization for energy-efficient timing error recovery in GPGPUs

“…For memory, 8T SRAM arrays utilize a tunable replica bits therefore enables reduction of the minimum operating voltage [7]. Similarly, in non-volatile memory area, resistive RAM (ReRAM/memristor) is a promising candidate at low power supply voltage [8]. For logic, error-detection sequential (EDS) [6] circuit sensors have been employed to reduce guardbanding in the designed circuits.…”