2021 IEEE 14th International Conference on ASIC (ASICON) 2021
DOI: 10.1109/asicon52560.2021.9620274
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A ReRAM-based 10T2R SRAM Using Power-off Recovery Function for Reducing Power

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“…This approach helps to prevent unnecessary write operations on SHE-MTJs when the data stored in the cross-coupled inverters change during continuous power on, thereby improving energy efficiency. The bitcell depicted in Figure 3e adds four clock-controlled power-gating transistors (M9~M12) to save energy, and it adopts the twoends nvSRAM scheme [81][82][83] with two RRAM devices in a bitcell to improve reliability in low-HRS/LRS scenarios through differential sensing [19]. Despite its larger area and energy consumption compared to single-end nvSRAM cells [84][85][86], this configuration offers a superior sense margin and restoration yield for emerging NVM technology.…”
Section: Design Considerations For Nvm In Mcumentioning
confidence: 99%
“…This approach helps to prevent unnecessary write operations on SHE-MTJs when the data stored in the cross-coupled inverters change during continuous power on, thereby improving energy efficiency. The bitcell depicted in Figure 3e adds four clock-controlled power-gating transistors (M9~M12) to save energy, and it adopts the twoends nvSRAM scheme [81][82][83] with two RRAM devices in a bitcell to improve reliability in low-HRS/LRS scenarios through differential sensing [19]. Despite its larger area and energy consumption compared to single-end nvSRAM cells [84][85][86], this configuration offers a superior sense margin and restoration yield for emerging NVM technology.…”
Section: Design Considerations For Nvm In Mcumentioning
confidence: 99%