An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration

A Survey of Emerging Memory in a Microcontroller Unit

“…A state-of-the-art MCU utilized four key design techniques to implement a 10.8 MB embedded STT-MRAM macro, which achieved the fastest random read access frequency and write throughput among reported Flash-replacement MRAMs [59]. However, the limited endurance of RRAM and reliability issues of MTJ impede their broader utilization [15,19,54]. PCM featured an attractive cell size of 0.019 F 2 and attained the largest capacity of 21 MB among the embedded NVMs presented in Table 1.…”

“…For instance, the cutting-edge ultra-low leakage MCU, leveraging 55 nm TFET-CMOS hybrid technology, achieved significant standby power reduction through innovative TFET-Gated-Ground SRAM and voltage-stacking techniques [62]. However, switching between active and standby modes consumes additional power for data transfer between volatile and nonvolatile memories [19,42,63]. Therefore, nvSRAM was proposed as a replacement for the traditional two-macro approach due to its high-speed parallel operation.…”

“…Therefore, nvSRAM was proposed as a replacement for the traditional two-macro approach due to its high-speed parallel operation. The NVM elements and SRAM part are integrated in an nvSRAM bitcell by a bit-to-bit connection instead of a macro-to-macro connection [19,64]. By storing commonly used routines in the nvSRAM, the startup latency and associated energy consumption from data movement can be eliminated, enabling more efficient edge computing applications [65].…”

“…Based on the emerging NVMs, nonvolatile static random-access memory (nvSRAM) is suggested as a replacement for the two-macro method (SRAM and Flash) because of its parallel operation and high speed [19]. The store operation of an nvSRAM bitcell involves, in nature, programming the nonvolatile elements according to the data held in the SRAM part.…”

“…Additionally, ensuring the reliability of real-time storage and restoration data in the nvSRAM is crucial for maintaining a successive workflow and service quality in MCUs. A bitcell-circuit-system co-design was employed to improve the reliability and scalability of a 64 KB RRAM-based nvSRAM, which was integrated into a 32-bit MCU and achieved a sub-0.1% raw bit error rate between the power outages [19]. Prior works have also investigated the possibility of utilizing the emerging NVM as an embedded Flash (eFlash) to enable rapid macro-to-macro backup and recall operations in the event of power loss [12,21,22].…”