A Replacement Strategy for Canary Flip-Flops

Kunitake, Yuji; Sato, Toshinori; Yasuura, Hiroto

doi:10.1109/prdc.2010.46

Cited by 11 publications

(2 citation statements)

References 4 publications

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“…The objective of [4], [5] is to minimize the overhead of adaptive body bias (ABB), but it assumes ABB is applied to all clusters. Another work [11] restricts variation sensors only at timing critical paths so that the overhead is not excessively large. However, it does not consider control or voltage generation overhead.…”

Section: Background and Related Workmentioning

confidence: 99%

Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits

Wang

2015

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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Adaptive design is a power-efficient approach to variation resilience in VLSI circuits. However, its implementation, especially that of fine-grained adaptivity, can easily result in large overhead. Although numerous previous works have demonstrated the effectiveness of adaptive design, very few works have emphasized its overhead control. In order to make adaptive design a truly practical approach, we develop a method that systematically optimizes adaptivity assignment with consideration of overhead reduction. At the same time, a variability aware gate implementation selection technique is investigated and applied in conjunction with the adaptivity assignment. Experimental results on benchmark circuits indicate that our approach can greatly decrease adaptivity overhead while satisfy performance and robustness constraints.

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Section: Background and Related Workmentioning

confidence: 99%

Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits

Wang

2015

2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

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“…These operations are processed with the help of different kind of normal or application specific MAC units. The Block diagram of a classical DSP is presented [13] in Fig. 1.…”

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confidence: 99%

An in-Situ Timing-Error Prediction and Prevention Technique for Variation-Tolerant Mac-Unit.

Singh¹,

Saha²,

Pahuja³

2017

IJAR

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…………………………………………………………………………………………………….... Introduction:-In deep submicron Integrated Circuits (IC) technologies, process-induced parameter variations cause performance fluctuations, which is an important challenge to be addressed. Due to this, the traditional worst-case methodology of design is no more effective as process variations require more design margins. To deal with this problem, the prediction of parameter variations can play a vital role in manufacturability of silicon devices [1,2,3]. Lower technology nodes are setting a trend of lowering supply-voltage and tremendous increase in clock frequency. These changes of voltage and temperature variations make the design more and more tedious. To achieve a robust design along with above discussed constraints, designers are focusing on Design for Manufacturability (DFM), which is a key to solve these serious problems. As the worst cases rarely occur, so it is always better for the designers to focus on typical cases, called as typical-case design methodology. In recent time, different typical-case design methodologies are proposed, such as Razor circuit [4][5]

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