An in-Situ Timing-Error Prediction and Prevention Technique for Variation-Tolerant Mac-Unit.

Abstract

…………………………………………………………………………………………………….... Introduction:-In deep submicron Integrated Circuits (IC) technologies, process-induced parameter variations cause performance fluctuations, which is an important challenge to be addressed. Due to this, the traditional worst-case methodology of design is no more effective as process variations require more design margins. To deal with this problem, the prediction of parameter variations can play a vital role in manufacturability of silicon devices [1,2,3]. Lower technology nodes are setting a trend of lowering supply-voltage and tremendous increase in clock frequency. These changes of voltage and temperature variations make the design more and more tedious. To achieve a robust design along with above discussed constraints, designers are focusing on Design for Manufacturability (DFM), which is a key to solve these serious problems. As the worst cases rarely occur, so it is always better for the designers to focus on typical cases, called as typical-case design methodology. In recent time, different typical-case design methodologies are proposed, such as Razor circuit [4][5]