A reliable static-logic-based 16:1 binary-tree multiplexer in 0.18 μm CMOS

Short, Kenneth L.; Trung, Nguyễn Thành; Kim, Soo-Won; Yoo, Jae-Tack

doi:10.1109/mwscas.2007.4488768

Cited by 2 publications

(4 citation statements)

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“…To implement MUXes with larger fan-in, tree-based cascade architectures are most often adopted [30][31][32][33][34][35][36]. For this reason, such a style has been also used in the design of 4:1 and 8:1 QCA MUXes [2,3], whose architectures are illustrated in Figure 2b and 2c, respectively.…”

Section: Background and Related Workmentioning

confidence: 99%

“…larger than 4:1) are crucial as fundamental blocks in several popular applications; few examples are the realization of lookup tables for special function units and the decoders in memory circuits [30][31][32][33][34][35][36]. larger than 4:1) are crucial as fundamental blocks in several popular applications; few examples are the realization of lookup tables for special function units and the decoders in memory circuits [30][31][32][33][34][35][36].…”

Section: Introductionmentioning

confidence: 99%

“…The novel designs here demonstrated fully exploit the intrinsic logic capabilities of the basic building block in the QCA domain: the Majority Gate. larger than 4:1) are crucial as fundamental blocks in several popular applications; few examples are the realization of lookup tables for special function units and the decoders in memory circuits [30][31][32][33][34][35][36]. A 16:1 multiplexer designed by applying the proposed recursive approach requires less than 1600 cells and consumes only 12 clock phases to complete the operation.…”

mentioning

confidence: 99%

“…The design of complex gates, such as multiplexers (MUXes), is not actually straightforward, and proper strategies have to be adopted at both logic and layout levels to improve performance and area behaviors.Large fan-in multiplexers (i.e. larger than 4:1) are crucial as fundamental blocks in several popular applications; few examples are the realization of lookup tables for special function units and the decoders in memory circuits [30][31][32][33][34][35][36]. This paper is focused on the design of efficient QCA-based large fan-in MUXes and proposes a novel approach that smartly exploits the majority logic function…”

mentioning

confidence: 99%

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Design of efficient QCA multiplexers

Cocorullo

Corsonello

Frustaci

et al. 2015

Circuit Theory & Apps

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A new methodology to realize efficient multiplexers using quantum-dot cellular automata (QCA) is presented in this paper. The novel designs here demonstrated fully exploit the intrinsic logic capabilities of the basic building block in the QCA domain: the Majority Gate. An efficient logic formulation is derived for the 4:1 multiplexing function that can be recursively applied to the realization of multiplexers with any fan-in, by adding in the worst-case path only one level of Majority Gate for each input doubling. A 16:1 multiplexer designed by applying the proposed recursive approach requires less than 1600 cells and consumes only 12 clock phases to complete the operation. INTRODUCTIONRecently the emerging technology based on quantum-dot cellular automata (QCA) has received a great deal of attention, and several solutions have been proposed to design efficient logic circuits, such as multiplexers [1-3], adders [4][5][6][7][8][9][10][11], multipliers [12-18] and comparators [19][20][21][22][23][24][25][26].The QCA nanostructure originally demonstrated in [27] uses a square cell with four quantum dots and two free electrons as the basic element to realize both logic structures and interconnections. The free electrons can tunnel through the dots within the cell, but, owing to Coulombic repulsion, they can lead to only two possible stable states, also named polarizations, that are associated with the binary states 1 and 0. Even though adjacent cells interact through electrostatic forces and tend to align their polarizations, QCA cells do not have intrinsic data flow directionality. The latter is provided by means of four clock signals clk x (with x ranging from 0 to 3), shifted by 90°from each other, that are progressively associated to the cells within a QCA design [28,29]. This clock scheme, named the zone clocking scheme, makes the QCA designs intrinsically pipelined, because each clock zone behaves like a D-latch.The fundamental logic gates inherently available within the QCA technology are the inverter and the majority gate (MG); non-elementary digital modules are designed combining instances of these basic gates and exploiting an efficient zone clocking scheme . The design of complex gates, such as multiplexers (MUXes), is not actually straightforward, and proper strategies have to be adopted at both logic and layout levels to improve performance and area behaviors.Large fan-in multiplexers (i.e. larger than 4:1) are crucial as fundamental blocks in several popular applications; few examples are the realization of lookup tables for special function units and the decoders in memory circuits [30][31][32][33][34][35][36]. This paper is focused on the design of efficient QCA-based large fan-in MUXes and proposes a novel approach that smartly exploits the majority logic function

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