A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms

Bolchini, Cristiana; Fossati, L.; Codinachs, David Merodio; Miele, Antonio; Sandionigi, Chiara

doi:10.1109/dft.2010.30

Cited by 10 publications

(6 citation statements)

References 14 publications

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“…The problem has been investigated in [1], [2], and [3]. The work presented in [1] proposes only a rough and not evaluated algorithm, since the focus is on the design of the overall engine managing fault tolerance. The reliability of the engine is guaranteed by periodically reading its configuration data, that is an expensive operation and subject to errors.…”

Section: Related Workmentioning

confidence: 99%

“…The observability of a fault is related to the probability of the fault to hit a used resource (P r ). In [5], the following formula has been proposed for computing P r : P r = dynamic cross section static cross section (1) where the static cross section is the total sensitive fraction of the device, and dynamic cross section is the operational fraction. The other element that should be taken into account is the latency, that is the time, related to the fault-error relation, occurring between the instant the fault occurs and the time an error is detected.…”

Section: A Adopted Fault Modelmentioning

confidence: 99%

“…The algorithm is devised to operate in a system composed of two elements, as in [1]: the logic implementing the actual application, and a module, called Reconfiguration Controller, implementing the fault classification and the recovery strategy.…”

Section: B Envisioned Systemmentioning

confidence: 99%

See 2 more Smart Citations

A reliable fault classifier for dependable systems on SRAM-based FPGAs

Bolchini

Sandionigi

Fossati

et al. 2011

2011 IEEE 17th International on-Line Testing Symposium

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This paper presents an algorithm for the discrimination of faults in FPGAs based on their recovery possibility; some faults can be recovered by reconfiguring the faulty part of the device, others have a destructive effect. After classification has been carried out, the suitable fault recovery strategy is applied, with the final aim of enabling the exploitation of FPGAs, in particular SRAM-based ones, for critical applications, such as the ones in the space environment. In this scenario, we investigate the reliable implementation of the fault classification algorithm, that can be so integrated in an overall reliable system.

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Section: Related Workmentioning

confidence: 99%

Section: A Adopted Fault Modelmentioning

confidence: 99%

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A reliable fault classifier for dependable systems on SRAM-based FPGAs

Bolchini

Sandionigi

Fossati

et al. 2011

2011 IEEE 17th International on-Line Testing Symposium

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“…• definition of a design methodology for the realization of systems able to mitigate SE effects in the programmable part of SoPC platforms, by exploiting both classical and new fault detection and tolerance techniques, together with reconfiguration features [27], [28], [29]; and • definition of a suitable controller architecture for the management of the reconfiguration phase used to recover from the detected soft errors [30], [31].…”

Section: Design Methodologies For Implementing Hardened Systems Onmentioning

confidence: 99%

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Bolchini

Miele

Sandionigi

et al. 2012

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for mission- and safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC)

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“…The diversity of FPGA architectures and the limited availability of documentation make these tests a non-trivial task. Such a reliable reconfiguration process is also required for approaches, which utilize reconfiguration to achieve reliable system operation [5][6][7].…”

Section: Introduction and System Overviewmentioning

confidence: 99%

Transparent structural online test for reconfigurable systems

Abdelfattah

Bauer

Braun

et al. 2012

2012 IEEE 18th International on-Line Testing Symposium (IOLTS)

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FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing.In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application.

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A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms

Cited by 10 publications

References 14 publications

A reliable fault classifier for dependable systems on SRAM-based FPGAs

A reliable fault classifier for dependable systems on SRAM-based FPGAs

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

Transparent structural online test for reconfigurable systems

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