A Reliable and Energy-Efficient Nonvolatile Ternary Memory Based on Hybrid FinFET/RRAM Technology

Yousefi, Aram; Eslami, Nima; Moaiyeri, Mohammad Hossein

doi:10.1109/access.2022.3211562

Cited by 12 publications

(3 citation statements)

References 37 publications

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“…RRAM cells are more compact, allowing for higher-density memory arrays, which can be advantageous in applications where space is limited. It is reported that a hybrid RRAM/FinFET technology memory cell with 3T1R array architecture has reduced the delay and power consumption [128]. Hsieh et al proposed a bipolar 14 nm node FinFET RRAM architecture and improved the ON/OFF window along with good endurance and retention performance.…”

Section: A Digital Circuit Interactionmentioning

confidence: 99%

FinFET to GAA MBCFET: A Review and Insights

Das,

Rajalekshmi,

James

2024

IEEE Access

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This review article presents a journey from Fin-shaped field effect transistor (FinFET) to gate-all-around multi-bridge channel field effect transistor (GAA MBCFET) technology, unraveling the evolution of semiconductor architectures. This article provides a concise yet insightful overview of the development of FinFET, exploring modified architectures, current trends, and associated constraints. The growing importance of other semiconductor materials instead of Si in FinFET or other technologies has been studied in detail. The article explores an emerging technology called 'GAA MBCFET', highlighting its advantages over FinFET. It also delves into the notable drawbacks and complex fabrication challenges associated with the upcoming GAA MBCFET technology. INDEX TERMS Gate-All-Around (GAA), Multi-Bridge Channel (MBC), Silicon on Insulator (SOI)

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Section: A Digital Circuit Interactionmentioning

confidence: 99%

FinFET to GAA MBCFET: A Review and Insights

Das,

Rajalekshmi,

James

2024

IEEE Access

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“…Unlike write latency, which can be managed using buffers * Authors to whom any correspondence should be addressed. and intelligent scheduling [3][4][5], read delay is highly influenced by the inherent memory mechanism, although temperature and supply voltage exhibit widespread effects on memory characteristics [6][7][8]. Research on read delay can lead to advancements in memory design.…”

Section: Introductionmentioning

confidence: 99%

Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism

Oh,

Jeon,

Shin

et al. 2024

Nanotechnology

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This study examines the memory and read delay characteristics of quasi-nonvolatile memory (QNVM) devices operating in a positive feedback mechanism through technology computer-aided design simulation. The QNVM devices exhibit a rapid operation speed of 5 ns, a significant sensing margin of approximately 8.0 μA, and a retention time of around 1 s without any external bias. These devices showcase an exceptionally brief read delay of 0.12 ns. The energy band diagrams during the memory operation are analysed to clarify the factors influencing the read delay. The write and standby conditions modulate the potential barrier height during the standby operation, thereby affecting the read delay. Moreover, the shorter rising time causes the reduction of the read delay. This study demonstrates that the QNVM device has the potential to resolve energy consumption and speed issues in nonvolatile memory devices.

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“…To investigate the system level's latency and writing energy, SPICE modeling on 1T-1R, dynamic random-access memory (DRAM), and resistive random-access memory (RRAM) (~1 Gb) have been reported [13]. The 2T-1R and 3T-1R configurations are also published to mitigate the SPC-induced operation errors while reducing the energy consumption [14][15][16][17]. Despite there are breakthroughs in circuit-and system-level studies, the device-level RRAM characteristics still lack investigation.…”

Section: Introductionmentioning

confidence: 99%

Direct-Grown Helical-Shaped Tungsten-Oxide-Based Devices with Reconfigurable Selectivity for Memory Applications

Chen

Huang²,

Sarkar³

et al. 2022

JLPEA

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In this study, a direct-grown helical-shaped tungsten-oxide-based (h-WOx) selection device is presented for emerging memory applications. The selectivity in the selection devices is from 10 to 103 with a low off-current of 0.1 to 0.01 nA. In addition, the selectivity of volatile switching in the h-WOx selection devices is reconfigurable with a pseudo RESET process on the one-time negative voltage operations. The helical-shaped selection devices with the glancing angle deposition (GLAD) method show good compatibility, low power consumption, good selectivity, and good reconfigurability for next-generation memory applications.

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A Reliable and Energy-Efficient Nonvolatile Ternary Memory Based on Hybrid FinFET/RRAM Technology

Cited by 12 publications

References 37 publications

FinFET to GAA MBCFET: A Review and Insights

FinFET to GAA MBCFET: A Review and Insights

Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism

Direct-Grown Helical-Shaped Tungsten-Oxide-Based Devices with Reconfigurable Selectivity for Memory Applications

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