A Reconfigurable Processor Architecture

Niyonkuru, Adronis; Eggers, Göran; Zeidler, Hans Christoph

doi:10.1007/3-540-46117-5_131

Cited by 3 publications

(1 citation statement)

References 2 publications

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“…1) includes fixed functional units and different sets of execution units which are swapped during program execution [9]. They are listed and described as follows:…”

Section: A Partial Runtime Reconfigurable Processormentioning

confidence: 99%

Designing a runtime reconfigurable processor for general purpose applications

Niyonkuru

Zeidler

18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.

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A superscalar microprocessor with a variable number of execution units which are dynamically configured during program execution has been modeled. The runtime behaviour of an executed application is determined using a Trace Cache and the most suitable hardware configuration is loaded dynamically. This paper discusses major design aspects of the ongoing implementation process based on a partial reconfiguration design flow. Thus, some microarchitectural components are put together to form a fixed module while different sets of execution units build up reconfigurable ones. The communication between fixed and reconfigurable modules is assured by Xilinx Bus Macros.

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“…1) includes fixed functional units and different sets of execution units which are swapped during program execution [9]. They are listed and described as follows:…”

Section: A Partial Runtime Reconfigurable Processormentioning

confidence: 99%

Designing a runtime reconfigurable processor for general purpose applications

Niyonkuru

Zeidler

18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.

View full text Add to dashboard Cite

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Spatiotemporal Modular Arrangement for Energy Efficient Reconfigurable SoCs

Kinoshita

Okamura

Takano

et al. 2013

2013 IEEE 7th International Symposium on Embedded Multicore Socs

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Energy Efficiency Improvement by Dynamic Reconfiguration for Embedded Systems

Kinoshita

Yamaguchi

Takano

et al. 2015

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper seeks to improve power-performance efficiency of embedded systems by the use of dynamic reconfiguration. Programmable logic devices (PLDs) have the competence to optimize the power consumption by the use of partial and/or dynamic reconfiguration. It is a non-exclusive approach, which can use other power-reduction techniques simultaneous, and thus it is applicable to a myriad of systems. The power-performance improvement by dynamic reconfiguration was evaluated through an augmented reality system that translates Japanese into English. It is a wearable and mobile system with a head-mounted display (HMD). In the system, the computing core detects a Japanese word from an input video frame and the translated term will be output to the HMD. It includes various image processing approaches such as pattern recognition and object tracking, and these functions run sequentially. The system does not need to prepare all functions simultaneously, which provides a function by reconfiguration only when it is needed. In other words, by dynamic reconfiguration, the spatiotemporal module-based pipeline can introduce the reduction of its circuit amount and power consumption compared to the naive approach. The approach achieved marked improvements; the computational speed was the same but the power consumption was reduced to around 1 6 .

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A Reconfigurable Processor Architecture

Cited by 3 publications

References 2 publications

Designing a runtime reconfigurable processor for general purpose applications

Designing a runtime reconfigurable processor for general purpose applications

Spatiotemporal Modular Arrangement for Energy Efficient Reconfigurable SoCs

Energy Efficiency Improvement by Dynamic Reconfiguration for Embedded Systems

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