A Reconfigurable IF to DC Sub-Sampling Receiver Architecture With Embedded Channel Filtering for 60 GHz Applications

Grave, Baptiste; Frappé, Antoine

doi:10.1109/tcsi.2013.2248791

Cited by 9 publications

(8 citation statements)

References 14 publications

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“…Complex sub-sampling has been proposed in [6] for 60 GHz using phaseshifted sampling clocks. In our system a complex-valued analytic representation of the IF signal in analog domain is generated by means of a wide-band 90…”

Section: A Ideal Casementioning

confidence: 99%

Fractionally spaced complex sub-nyquist sampling for multi-gigabit 60 GHz wireless communication

Preyss

Koestler

Burg

2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Abstract-A novel analog front-end architecture based on complex subnyquist sampling for the intermediate frequency (IF) stage of a mmWave receiver is proposed. With this front-end, the use of a wideband hybrid coupler and two half-rate analog-to-digital converters (ADCs) allow for a flexible placement of the IF. It is shown that digital compensation of the impairments introduced by the non-ideal 90 • hybrid coupler is required to use high modulation orders. Further a digital signal processing (DSP) architecture is presented which performs equalization of a fractionally spaced sub-sampled IF signal in frequency domain (FD) and integrates the compensation of the impairments with low overhead. Based on this DSP architecture a working 60 GHz single-carrier link is demonstrated. Measurement results show the feasibility of 256 QAM modulated transmission with a bandwidth of up to 1.8 GHz and a resulting raw data rate of 12.8 Gb/s using our frontend architecture with the digital FD compensation.

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Section: A Ideal Casementioning

confidence: 99%

Fractionally spaced complex sub-nyquist sampling for multi-gigabit 60 GHz wireless communication

Preyss

Koestler

Burg

2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

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“…The reader is addressed to [7] for an extended justification of the architecture and detailed explanation of its operation Each path (Quadrature or In phase) is composed of 4 paths (A through D, detailed in Figure 3) working in an interleaved scheme for continuous operation.…”

Section: Core Architecture Of the Subsamplermentioning

confidence: 99%

“…In order to reach high sensitivity, the sampling instant should be set with a sub-picosecond precision [7]. This target cannot be reached simply by adding pairs of inverters because the delay of a simple inverter is around 8 ps in the targeted technology.…”

Section: B Sampling Instant Settingmentioning

confidence: 99%

“…The duty cycle of the input clock should be set to 50% with a precision of 1% to create the correct sampling window [7]. State of the art on duty cycle regulators (DCR) mainly focuses on high-speed locking solutions for low frequency clocks (up to 2 GHz).…”

Section: Duty Cycle Regulationmentioning

confidence: 99%

“…Recent research on RF receivers in the low GHz range has focused on low cost, low power and reconfigurable solutions, using sub-sampling receivers as an attractive solution in terms of area and power consumption [5] [6]. Pushing these concepts for 60 GHz communication systems, a system-level study for a receiver including an IF subsampling stage has been proposed in [7] in which a particular arrangement of the frequency plan allows embedded anti-alias filtering. This paper presents a 28 nm CMOS implementation of an IF subsampler suitable for heterodyne 60 GHz receivers.…”

Section: Introductionmentioning

confidence: 99%

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Subsampling techniques applied to 60 GHz wireless receivers in 28 nm CMOS

Grave

Frappé

2014

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

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This paper presents the architecture, the implementation details and the measurement results of an IF to DC subsampler for 60 GHz applications. The proposed subsampler performs downconversion, IQ demodulation and out-of-band filtering within a unique operation. An 802.11ad (WiGig) channel at a fixed 21.12 GHz IF frequency is subsampled using a 7.04 GHz clock. The 1.76 GS/s analog to digital conversion is directly performed in baseband after FIR filtering and decimation. The charge domain subsampler and FIR filter provide additional immunity to perturbations at no extra hardware cost. Digitally controlled delay lines set the phase of the sampling clock to reach the best sampling instant. In conclusion, subsampling-based back-ends can be promising candidates for low power, low cost and digitally synchonized receiver architectures

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A mmW low power VCO with high tuning range in 28nm FDSOI CMOS technology

Vallet

Richard

Deval

et al. 2014

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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A 28nm FDSOI CMOS low power VCO working at 40 GHz frequency is presented in this paper. The VCO core only consumes 6mW from a 1 V supply voltage. A wide tuning range of 18.5 % from 38.3 GHz to 46.1 GHz is reached with a tuning voltage from 0 to 1 V. A phase noise higher than -120.5 dBc/Hz at 10 MHz offset has been observed after post-layout simulations. A variable inductance approach has been chosen in order to maintain a sufficiently low phase noise despite significant constraints caused by the advanced technology nodes and the large tuning range needed. Index Terms-lowpower VCO, mmW, 40GHz, 28nm FDSOI, Wifi-WiGig convergence, wide tuning range 978-1-4799-4242-8/14/$31.00 c 2014 IEEE

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A Reconfigurable IF to DC Sub-Sampling Receiver Architecture With Embedded Channel Filtering for 60 GHz Applications

Cited by 9 publications

References 14 publications

Fractionally spaced complex sub-nyquist sampling for multi-gigabit 60 GHz wireless communication

Fractionally spaced complex sub-nyquist sampling for multi-gigabit 60 GHz wireless communication

Subsampling techniques applied to 60 GHz wireless receivers in 28 nm CMOS

A mmW low power VCO with high tuning range in 28nm FDSOI CMOS technology

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