Subsampling techniques applied to 60 GHz wireless receivers in 28 nm CMOS

Abstract

This paper presents the architecture, the implementation details and the measurement results of an IF to DC subsampler for 60 GHz applications. The proposed subsampler performs downconversion, IQ demodulation and out-of-band filtering within a unique operation. An 802.11ad (WiGig) channel at a fixed 21.12 GHz IF frequency is subsampled using a 7.04 GHz clock. The 1.76 GS/s analog to digital conversion is directly performed in baseband after FIR filtering and decimation. The charge domain subsampler and FIR filter provide additional immunity to perturbations at no extra hardware cost. Digitally controlled delay lines set the phase of the sampling clock to reach the best sampling instant. In conclusion, subsampling-based back-ends can be promising candidates for low power, low cost and digitally synchonized receiver architectures