A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS

Abstract

In modern ICs, the trend of integrating more on-chip memories on a die has led SRAMs to account for a large fraction of total area and energy of a chip. Therefore, designing memories with dynamic voltage scaling (DVS) capability is important since significant active as well as leakage power savings can be achieved by voltage scaling. However, optimizing circuit operation over a large voltage range is not trivial due to conflicting trade-offs of low-voltage (moderate and weak inversion) and high-voltage (strong inversion) transistor characteristics. Specifically, low-voltage operation requires various assist circuits for functionality which might severely impact high-voltage performance. Reconfigurable assist circuits provide the necessary adaptability for circuits to adjust themselves to the requirements of the voltage range that they are operating in. This paper presents a 64 kb reconfigurable SRAM fabricated in 65 nm low-power CMOS process operating from 250 mV to 1.2 V. This wide supply range was enabled by a combination of circuits optimized for both subthreshold and above-threshold regimes and by employing hardware reconfigurability. Three different write-assist schemes can be selectively enabled to provide write functionality down to very low voltage levels while preventing excessive power overhead. Two different sense-amplifiers are implemented to minimize sensing delay over a large voltage range. A prototype test chip is tested to be operational at 20 kHz with 250 mV supply and 200 MHz with 1.2 V supply. Over this range leakage power scales by more than 50 X and a minimum energy point is achieved at 0.4 V with less than 0.1 pJ/bit/access.

Benchmarking of Standard-Cell Based Memories in the Sub-$V_{\rm T}$ Domain in 65-nm CMOS Technology

“…Unless otherwise stated, the energy is given for f max at V DDmin . All sub-V T SRAM designs [8]- [10] realized in a 65-nm CMOS technology have V DDmin ≥ 300 mV. Monte Carlo simulations indicate that SCMs mapped to the same technology should operate reliably at least down to the same minimum supply voltage.…”

Characterization of 9T SRAM Cell at Various Process Corners at Deep Sub-micron Technology for Multimedia Applications

“…So, different topologies of SRAM cell have been implemented at various technologies to improve the data stability and leakage power consumption. Various topologies of SRAM cell has been introduced, 7T SRAM cell in which a read static noise margin is achieved by cutting off a pull down path during read operation but has limited write capability due to single end write operations [6], [7].8T SRAM cell which is one of the popular topology which increases the stability but has its own limitation. In this paper the limitation of 8T has been removed and alternative topologies have been discussed to increase the stability.…”

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS

“…Several research groups have proposed 8-transistor (8T) [1,2] or 10-transistor (10T) [3] SRAM bitcells reliably operating in the sub-V T domain. However, such sub-V T SRAM macros still have high leakage currents often dominating the leakage power of ultra-low-power (ULP) systems.…”

“…Standard-cell based memories (SCMs) are an interesting alternative to full-custom sub-V T SRAM macros in order to significantly reduce the design effort, ensure reliability, and even reduce the area cost for storage capacities smaller than a few kb [5]. However, as many SRAM macros [1][2][3], the SCMs presented in [5] suffer from high leakage currents, as they are implemented with latches from a commercial standard-cell library, which is primarily optimized for speed, but not for leakage.…”