Characterization of 9T SRAM Cell at Various Process Corners at Deep Sub-micron Technology for Multimedia Applications

Abstract

Abstract-In the past decades CMOS IC technologies have been constantly scaled down and at present they aggressively entered in the nanometer regime. Amongst the wide-ranging variety of circuit applications, integrated memories especially the SRAM cell layout has been significantly reduced. As it is very well know the reduction of size of CMOS involves an increase in physical parameters variation, this is a factor which has a direct impact on SRAM cell stability. Polysilicon and diffusion critical dimensions (CD) together with implant variations are the main causes of mismatch in SRAM cells. SRAM memory cells have always been designed to occupy the minimum amount of silicon area consistent with the performance and reliability required. Today's system on Chip (SoC) trends result in a major percentage of the total die area being dedicated to memory blocks, consequently making SRAM parameter variations dominate the overall circuit parameter characteristics, including leakage, process variation effects, etc. The reliability is usually measured by static noise margin, SNM [1], and write trip point simulations and measurements. In this paper we have analyzed the stability of the 9T SRAM cell at SS, FF, TT, FS, SF corners. The simulations have been done at 45nm technology.Index Terms-SOCs, Embedded SRAM, Scaling, Deep submicron level. I. INTRODUCTIONSubthreshold leakage and gate current are not the only issues that have to be deal at a functional level, but at the same time the power management issues of chips for high-performance circuits such as microprocessors, digital signal processors, and graphics processing units are also necessary. Power management is also a challenge in mobile/multimedia applications. Device variations causing device mismatch for several reasons make the memory more sensitive in terms of stability. For stable read and write, the memory cells must be able to keep the stored state when accessed for reading but quickly change state when accessed for writing. These conflicting needs are even more difficult to achieve with the process variations of sub-100 nm processes.As the lithography shrinks, the device variations are becoming an ever increasing concern. With the sub-100 nm processes, statistical variations need to be included in the SRAM cell and SRAM block analysis to attain circuit designs with sufficient yield and performance within a defined limited area and power budget. On the contrary, the transistor and SRAM bit cell size reduction driven by the technology scaling has also made it even more challenging to maintain a sufficient cell stability margin while keeping the same scaling pace of access time and cell size as the mismatching of threshold voltage (Vt) between cross-coupled MOSFET pairs becomes larger and larger [1], [2], [3]. To maintain sufficient margins for read and write stability and read cell current has become challenging as Vdd has to be scaled down in order not only to meet the requirements for device scaling and power savings but also to keep the logic operating voltage c...

Dynamic Noise Margin Analysis of a Low Voltage Swing 8T SRAM Cell for Write Operation

“…This method, however, has never been used alone on real SRAMs, because it suffers from degradation of device reliability since the oxide of the pass-gate is over-stressed. A number of recent literatures also presents on the static and dynamic stability analyses of 6T, 7T, 8T, 9T SRAM cells for read and write operations [9], [10], [11], [12].…”

Design And Implementation of 8T SRAM cell for Analysis of DC Noise Margin during Write Operation

“…Most of these works rely on device equations to solve for parameters such as SNM, read disturbance and inverter trip-point. A number of recent literatures present the static and dynamic stability analyses of 6T, 7T, 8T, 9T SRAM cells for read and write operations [9][10][11][12]. All these papers used the butter fly diagrams to calculate the static noise margin (SNM) of the cross coupled inverters used in the SRAM cell for storing the data.…”