A Realizable Overlay Virtual Metrology System in Semiconductor Manufacturing: Proposal, Challenges and Future Perspective

Abstract

Integrated circuits (IC) are fabricated on a wafer through stacked layers of circuit patterns. To ensure proper functionality, the overlay of each pattern layer must be within the tolerance. Inspecting each wafer's overlay is unrealistic and impractical. Hence, wafers are selectively inspected at metrology stations through sampling strategies. With virtual metrology (VM), the metrology quality of the uninspected wafers can be estimated. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a VM to estimate the overlay of the photolithography process is envisioned. Past researches on overlay VM leveraged fault detection and classification (FDC) data to estimate the overlay errors. As such, for fabs in the progress of completing their FDC development for photolithography equipment, a different modeling approach is required to realize an overlay VM that sustains the production line until FDC data can be leveraged for VM. With practical gaps that must be addressed in real fabs, this paper focuses on realizing an overlay VM for the photolithography process without leveraging FDC data. Therefore, the objectives of this paper are two folds: First, to identify the research challenges towards realizing the overlay VM. Second, to propose the future research perspectives of the envisioned overlay VM. Based on the future research perspectives, a two-steps overlay VM modeling approach utilizing data mining techniques is proposed toward realizing the envisioned overlay VM system. The proposed approach first classifies the process stability at the wafer lot level, and subsequently, performs overlay error estimations for wafers in the wafer lots classified with stable process. Linear regression models are proposed to perform overlay error estimations in this work to augment the interpretability of the overlay VM.

Virtual Metrology in Semiconductor Fabrication Foundry Using Deep Learning Neural Networks

“…This work employs the methodology proposed in [11] as the methodology to evaluate the performance of the CNN in predicting the overlay errors of wafers. The authors of [11] proposed a joint-modelling of novelty detection task and regression task.…”

“…This work employs the methodology proposed in [11] as the methodology to evaluate the performance of the CNN in predicting the overlay errors of wafers. The authors of [11] proposed a joint-modelling of novelty detection task and regression task. The joint-modelling first perform novelty detection to filter out wafers that are predicted to be faulty from entering the regression task.…”

“…In [11], the authors proposed a lot-level modelling approach to address real fab condition where process condition could not be sampled at high frequency due to various limitations and events. From the literature review, [12] categorized high data sampling frequency for fabrication process as sampling frequencies at 1 Hertz (Hz) or higher.…”

“…The input to the CNN can be written as Equation (1). The features denoted by will be derived using the same statistical descriptors presented by [11].…”

Comprehensive Data Collection Device for Plasma Equipment Intelligence Studies

“…However, most plasma processes currently used in industry are done so without a complete understanding of the physical and chemical properties of the plasma. Therefore, a comprehensive understanding of plasma characteristics is needed to improve process reproducibility and equipment operation safety [4,5]. Increased understanding can help develop next-generation plasma process equipment and apply it to advanced process and equipment control.…”