A real-time H.264 MP decoder based on a DM642 DSP

Pescador, F.; Garrido, M.J.; Sanz, C.; Juárez, E.; Rodríguez, M.; Samper, David

doi:10.1109/icecs.2007.4511223

Cited by 6 publications

(4 citation statements)

References 9 publications

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“…So 4×4-based MC is not suited for DSP based decoder. In paper [7], sub-block-based MC is proposed to improve transport efficiency. But, small block based MC results in page missing [8] frequently.…”

Section: A Novel Approach For Transferring Reference Datamentioning

confidence: 99%

Optimization techniques for a DSP based H.264 decoder

Chen

2010

2010 2nd International Conference on Signal Processing Systems

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In this paper, two kinds of optimization techniques were proposed to enhance the performance of H.264 decoder that based on a DSP processor. One approach is to transfer reference data via DMA with a novel approach, which can utilize external bus efficiently. The other approach is to perform the block-based de-blocking filter, which minimizes the times of external memory access. The experimental results show that the proposed solution can improve the H.264 decoding speed by almost 58%. The optimized H.264 decoder can achieve the CIF @25Hz video decoding on a Blackfin 533 processor when operating at 526MHz clock.

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Section: A Novel Approach For Transferring Reference Datamentioning

confidence: 99%

Optimization techniques for a DSP based H.264 decoder

Chen

2010

2010 2nd International Conference on Signal Processing Systems

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“…Researchers have presented methods to efficiently manage bit manipulation operations with results obtained on general purpose processor architectures [8], DSPs [1,5] or applications without real-time constraints [4]. This leads to a lack of exploration of real-time applications implemented on codesign architectures even though they are more and more used.…”

Section: Related Workmentioning

confidence: 99%

“…Usually these architectures are based on DSPs [1], ASICs [2], or high performance processors. However, DSPs and embedded-processors still face limitations in terms of computing power for applications that require high performance.…”

Section: Introductionmentioning

confidence: 99%

Design of a processor optimized for syntax parsing in video decoders

Siret

Nezan

Rhatay³

2011

Proceedings of the 2011 Conference on Design &Amp; Architectures for Signal &Amp; Image Processing (DASIP)

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Heterogeneous platforms aim to offer both performance and flexibility by providing designers processors and programmable logical units on a single platform. Processors implemented on these platforms are usually soft-cores (e.g. Altera NIOS) or ASIC (e.g. ARM Cortex-A8). However, these processors still face limitations in terms of performance compared to full hardware designs in particular for real-time video decoding applications. We present in this paper an innovative approach to improve performance using both a processor optimized for the syntax parsing (an Application-Specific Instruction-set Processor) and a FPGA. The case study has been synthesized on a Xilinx FPGA at a frequency of 100 MHz and we estimate the performance that could be obtained with an ASIC.

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“…They have concentrated on how to meet video compression and processing requirements since video processing require significant amount of computation power. So they proposed solutions, either Application Specific Integrated Circuit (ASIC) [2][3] or processor-based [4][5][6][7][8][9][10][11] solutions, to achieve this target. The ASIC solution offers the best speed performance.…”

Section: Introductionmentioning

confidence: 99%

A system architecture exploration on the configurable HW/SW co-design for H.264 video decoder

Jian

Chu

Huang

et al. 2009

2009 IEEE International Symposium on Circuits and Systems

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In this paper we focus on the design methodology to propose a design that is more flexible than ASIC solution and more efficient than the processor-based solution for H.264 video decoder. We explore the memory access bandwidth requirement and different software/hardware partitions so as to propose a configurable architecture adopting a DEM (Data Exchange Mechanism) controller to fit the best tradeoff between performance and cost when realizing H.264 video decoder for different applications. The proposed architecture can achieve more than three times acceleration in performance.

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A real-time H.264 MP decoder based on a DM642 DSP

Cited by 6 publications

References 9 publications

Optimization techniques for a DSP based H.264 decoder

Optimization techniques for a DSP based H.264 decoder

Design of a processor optimized for syntax parsing in video decoders

A system architecture exploration on the configurable HW/SW co-design for H.264 video decoder

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