A read-disturb-free and write-ability enhanced 9T SRAM with data-aware write operation

Lv, Jiaxun; Wang, Zilin; Huang, Maohang; He, Yajuan

doi:10.1080/00207217.2021.1908614

International Journal of Electronics

2021

DOI: 10.1080/00207217.2021.1908614

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A read-disturb-free and write-ability enhanced 9T SRAM with data-aware write operation

Jiaxun Lv

Zilin Wang

Maohang Huang

et al.

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Cited by 4 publications

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“…Authors in Ref. 11 have presented an 9 T SRAM cell to improve both RSNM and WSNM and to eliminate the HSD issue. The presence of two seriesconnected N-type transistors in its write path prevents significantly improving write performance.…”

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confidence: 99%

A Stable Low Leakage Power SRAM with Built-In Read/Write-Assist Scheme using GNRFETs for IoT Applications

Abbasian¹,

Mirzaei²,

Sofimowloodi³

2022

ECS J. Solid State Sci. Technol.

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Design of circuits using graphene nanoribbon field-effect transistors (GNRFETs), as promising next-generation devices, can improve total performance of a chip due to offering excellent properties. However, GNRFETs are in the early stage of design, and the studies of process-voltage-temperature (PVT) variations on their performance are very crucial. Here, we aimed to design, simulate, and evaluate a novel stable fully differential 12T (SFD12T) SRAM using GNRFETs under PVT variations. Simulation results in 16-nm GNRFET technology at 0.5 V show that the proposed design improves read stability/writability by 2.11×/1.09× compared to fully differential 8T (FD8T: as a basic cell) due to using built-in read/write-assist scheme, which forces the ‘0’ storing node to ground during a read operation and cuts pull-down path off during a write operation, respectively. An improvement of at least 4.79% (18.55% compared to FD8T) in leakage power is achieved due to stacking of transistors. The fourth-best read/write energy among eight studied SRAMs is related to the proposed design. In addition, it can support the bit-interleaving architecture because it eliminates half-select disturbance issues. Generally, the proposed design is the best SRAM from the figure of merit (FOM) point of view, so it can be an optimal choice for Internet-of-Things applications.

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confidence: 99%

A Stable Low Leakage Power SRAM with Built-In Read/Write-Assist Scheme using GNRFETs for IoT Applications

Abbasian¹,

Mirzaei²,

Sofimowloodi³

2022

ECS J. Solid State Sci. Technol.

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A FinFET-based low-power, stable 8T SRAM cell with high yield

Mani,

Nimmagadda,

Basha

et al. 2024

AEU - International Journal of Electronics and Communications

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A low power Schmitt-trigger driven 10T SRAM Cell for high speed applications

Soni,

Pandey

2024

Integration

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A read-disturb-free and write-ability enhanced 9T SRAM with data-aware write operation

Cited by 4 publications

References 13 publications

A Stable Low Leakage Power SRAM with Built-In Read/Write-Assist Scheme using GNRFETs for IoT Applications

A Stable Low Leakage Power SRAM with Built-In Read/Write-Assist Scheme using GNRFETs for IoT Applications

A FinFET-based low-power, stable 8T SRAM cell with high yield

A low power Schmitt-trigger driven 10T SRAM Cell for high speed applications

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