A ratio-independent algorithmic pipeline analog-to-digital converter

Hatanaka, S.; Taniguchi, K.

doi:10.1109/icecs.2001.957750

Cited by 5 publications

(4 citation statements)

References 1 publication

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“…Other ratio-independent circuits have been reported which only require two op-amps and four clock phases, as those presented in [13,14,17]. However, in [13,14] the main amplifier cannot be shared between two successive pipelined stages.…”

Section: Discussionmentioning

confidence: 96%

“…However, in [13,14] the main amplifier cannot be shared between two successive pipelined stages. It could be argued that, if the first amplifier is shared between two stages, its input referred offset will not be cancelled because it is always active [4].…”

Section: Discussionmentioning

confidence: 99%

“…Other techniques reduce the sensibility to capacitor ratio using the so called ''capacitor error averaging'' [8][9][10]. However, these techniques do not remove completely the mismatch error, while the ratio independent techniques [11][12][13][14] do.…”

Section: Introductionmentioning

confidence: 99%

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A new capacitor-ratio and offset independent residue amplifier

Gmili

Muñoz

Torralba

et al. 2010

Analog Integr Circ Sig Process

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Matching accuracy of capacitors at the first stage of the residue amplifier limits the overall resolution in pipelined analog-to-digital converters. A new residue amplifier is presented in this paper which is inherently insensitive not only to capacitor ratio but also to amplifier offset voltage and gain errors. Experimental and simulation results are provided to show how the proposed technique senses and compensates these errors.

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Section: Discussionmentioning

confidence: 96%

Section: Discussionmentioning

confidence: 99%

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A new capacitor-ratio and offset independent residue amplifier

Gmili

Muñoz

Torralba

et al. 2010

Analog Integr Circ Sig Process

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“…In a cyclic ADC, the residue signal is recursive, thus only one stage is required. Therefore, a cyclic ADC is an attractive choice to meet the stringent requirements for chip area and power consumption [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

2014

Analog Integr Circ Sig Process

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This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at lowvoltage power supply. The prototype ADC, fabricated in TSMC 0.18 lm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.

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A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique

Wang

Inoue

2008

IEICE Transactions on Fundamentals of Electronics, Communicatio

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A ratio-independent algorithmic pipeline analog-to-digital converter

Cited by 5 publications

References 1 publication

A new capacitor-ratio and offset independent residue amplifier

A new capacitor-ratio and offset independent residue amplifier

A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique

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