A RAM cache approach using host memory buffer of the NVMe interface

Hong, Jin-Gi; Han, Sangwoo; Chung, Eui-Young

doi:10.1109/isocc.2016.7799757

Cited by 3 publications

(2 citation statements)

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“…In [22], Hong et al used a host DRAM as a data cache instead of an address mapping table cache by modifying the NVMe command process and adding a direct memory access (DMA) path between system memory and the host DRAM. The proposed scheme improved the I/O performance by 23% for sequential writes compared to an architecture with internal DRAM in the SSD.…”

Section: Plos Onementioning

confidence: 99%

HMB in DRAM-less NVMe SSDs: Their usage and effects on performance

Kim

2020

PLoS ONE

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Solid-state drives (SSDs) that do not have internal dynamic random-access memory (DRAM) are being widely spread for client SSD and embedded SSD markets in recent years because they are cheap and consume less power. Obviously, their performance is lower than conventional SSDs because they cannot exploit advantages of DRAM in the controller. However, this problem can be alleviated by using host memory buffer (HMB) feature of Non-Volatile Memory Express (NVMe), which allows SSDs to utilize the DRAM of host. In this paper, we show that commercial DRAM-less SSDs clearly exhibit worse I/O performance than SSDs with internal DRAM, but this can be improved by using the HMB feature. We also present methods that reveal how the host memory buffer is used in commercial DRAM-less SSDs to improve I/O performance. Through extensive experiments, we conclude that DRAM-less SSDs evaluated in this study mainly exploit the host memory buffer as an address mapping table cache rather than a read cache or write buffer to improve I/O performance.

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Section: Plos Onementioning

confidence: 99%

HMB in DRAM-less NVMe SSDs: Their usage and effects on performance

Kim

2020

PLoS ONE

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“…They demonstrated that utilizing the HMB boosts the input/output operations per second (IOPS) performance significantly compared to other DRAMless solutions. In [8], Hong et al used a host DRAM as a data cache instead of an address mapping table cache by modifying the NVMe command process and adding a direct memory access (DMA) path between the system memory and the host DRAM. The proposed scheme improved the I/O performance by 23% for sequential writes over the architecture with internal DRAM in the SSD.…”

Section: B Hmb Of Nvme Interfacementioning

confidence: 99%

HMB-SSD: Framework for Efficient Exploiting of the Host Memory Buffer in the NVMe SSD

2019

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Host Memory Buffer (HMB) is a highlighted feature of the Non-Volatile Memory Express (NVMe) protocol, which is the state-of-the-art storage interface for emerging storage devices such as Solid-State Drives (SSDs). HMB enables the underlying storage to make use of a portion of host memory for caching their address mapping information and/or user data, so that they can overcome the limited capacity of memory within the storage. This technology opens an opportunity to optimize the I/O performance costeffectively by sharing the ample host memory with the severely resource-constrained device. However, it is challenging to study the HMB-based optimization techniques in the practical system because there is no SSD development platform supporting the HMB feature as well as the commercial SSD products veil their internals, not allowing a custom extension. Motivated by this limitation, this paper presents an HMB-supported SSD development platform called HMB-SSD, which is built by faithfully extending an open-source SSD emulator. HMB-SSD enables to easily integrate and evaluate I/O techniques for the HMB feature in an SSD emulator, which closely mimics the behavior of real devices. We demonstrate the proper operation of our platform and the efficacy of the HMB feature with a case study on write buffering. In our empirical study, the SSD storage achieves a large performance benefit with the HMB-based write buffer, yielding up to 86.2% better performance than that of without it.

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Design of High-performance Heterogeneous Integrated Circuits

Melikyan

2023

Machine Learning-Based Design and Optimization of High-Speed Circuits

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A RAM cache approach using host memory buffer of the NVMe interface

Cited by 3 publications

References 1 publication

HMB in DRAM-less NVMe SSDs: Their usage and effects on performance

HMB in DRAM-less NVMe SSDs: Their usage and effects on performance

HMB-SSD: Framework for Efficient Exploiting of the Host Memory Buffer in the NVMe SSD

Design of High-performance Heterogeneous Integrated Circuits

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