HMB in DRAM-less NVMe SSDs: Their usage and effects on performance

Kim, Kyusik; Kim, Taeseok

doi:10.1371/journal.pone.0229645

Cited by 5 publications

(2 citation statements)

References 10 publications

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“…HPB [18] uses a part of the host system memory as a map cache to improve random read performance in a mobile environment with only SRAM. In [19], the host memory buffer, which is one of the characteristics of NVMe, is utilized to improve the performance of the DRAM-less SSD, and a map cache is concluded as an optimal usage among several other methods. HAT [20] stores the entire mapping table in a phase-change memory (PCM) to eliminate the time required to access the flash for fetching mapping information.…”

Section: B Improving Performance Of Flash Storage With Map Cachementioning

confidence: 99%

Internal Task-Aware Command Scheduling to Improve Read Performance of Embedded Flash Storage Systems

et al. 2021

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Many NAND flash storage systems access flash memories by generating flash commands to process input/output (I/O) requests from a host system. Because the order in which flash commands are processed affects the I/O performance, command scheduling has been performed in previous studies to prioritize flash read commands for improving the read performance. However, in addition to the flash commands for accessing user data requested by the host, flash commands for internal tasks that improve the I/O performance and operation efficiency of the flash storage are issued. Particularly in embedded flash storage, the flash commands by the map cache management have a significant influence on the latency of I/O requests. The processing time of the I/O request depends on the execution time of the flash commands for mapping information and the flash commands for user data. In this paper, we propose command scheduling to improve read performance to address the occurrence of map flash commands. Priority is given to the flash read and program command from the read request, and among these commands, the flash command originating from the read request, which has a shorter processing time, is executed first. Consequently, the waiting time of the flash command is reduced, thereby improving the read latency. Experiments conducted with real workloads show that the proposed scheduling scheme reduces the average read latency by up to 51% compared with the existing scheduling scheme and demonstrates an effective performance improvement in a small map cache.INDEX TERMS Command scheduling, map cache, address translation, flash translation layer, NAND flash storage, NAND flash memory.

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Section: B Improving Performance Of Flash Storage With Map Cachementioning

confidence: 99%

Internal Task-Aware Command Scheduling to Improve Read Performance of Embedded Flash Storage Systems

et al. 2021

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“…Apart from NAND flash arrays that hold data, an SSD device commonly has a faster but small amount of dynamic random access memory (DRAM) that acts as a cache for I/O operations. For instance, the Silicon Armor SP A80 SSD is equipped with 512GB flash array and 8MB∼480MB cache [3].…”

Section: Introductionmentioning

confidence: 99%

Unifying Temporal and Spatial Locality for Cache Management inside SSDs

Sha

Cai

Liao

et al. 2022

2022 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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To ensure better I/O performance of solid-state drivers (SSDs), a dynamic random access memory (DRAM) is commonly equipped as a cache to absorb overwrites or writes, instead of directly flushing them onto underlying SSD cells. This paper focuses on the management of the small amount cache inside SSDs. First, we propose to unify both factors of temporal and spatial locality of user applications by employing the visibility graph technique, for directing cache management. Next, we propose to support batch adjustment of adjacent or nearby (hot) cached data pages by referring to the connection situations in the visibility graph of all cached pages. At last, we propose to evict the buffered data pages in batches, to maximize the internal flushing parallelism of SSD devices, without worsening I/O congestion. The trace-driven simulation experiments show that our proposal can yield improvements on cache hits by more than 2.8%, and the overall I/O latency by 20.2% on average, in contrast to conventional cache schemes inside SSDs.

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