A quasi-power-gated low-leakage stable SRAM cell

Nair, Pradeep S.; Eratne, Savithra; John, Eugene

doi:10.1109/mwscas.2010.5548705

Cited by 12 publications

(5 citation statements)

References 7 publications

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“…Many circuit design and architectural solutions, such as V DD scaling [12], power-gating [15], and body-biasing [11], have been invented to reduce the standby power of caches. However, these techniques are becoming less efficient as technology continues to scale, causing the transistor's leakage current to increase exponentially.…”

Section: Introductionmentioning

confidence: 99%

Multi retention level STT-RAM cache designs with a dynamic refresh scheme

Sun

et al. 2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

191

156

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Spin-transfer torque random access memory (STT-RAM) has received increasing attention because of its attractive features: good scalability, zero standby power, non-volatility and radiation hardness. The use of STT-RAM technology in the last level on-chip caches has been proposed as it minimizes cache leakage power with technology scaling down. Furthermore, the cell area of STT-RAM is only 1/9 ∼ 1/3 that of SRAM. This allows for a much larger cache with the same die footprint, improving overall system performance through reducing cache misses. However, deploying STT-RAM technology in L1 caches is challenging because of the long and power-consuming write operations. In this paper, we propose both L1 and lower level cache designs that use STT-RAM. In particular, our designs use STT-RAM cells with various data retention time and write performances, made possible by different magnetic tunneling junction (MTJ) designs. For the fast STT-RAM bits with reduced data retention time, a counter controlled dynamic refresh scheme is proposed to maintain the data validity. Our dynamic scheme saves more than 80% refresh energy compared to the simple refresh scheme proposed in previous works. A L1 cache built with ultra low retention STT-RAM coupled with our proposed dynamic refresh scheme can achieve 9.2% in performance improvement, and saves up to 30% of the total energy when compared to one that uses traditional SRAM. For lower level caches with relative large cache capacity, we propose a data migration scheme that moves data between portions of the cache with different retention characteristics so as to maximize the performance and power benefits. Our experiments show that on the average, our proposed multi retention level STT-RAM cache reduces 30 ∼ 70% of the total energy compared to

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Section: Introductionmentioning

confidence: 99%

Multi retention level STT-RAM cache designs with a dynamic refresh scheme

Sun

et al. 2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

191

156

View full text Add to dashboard Cite

show abstract

“…This reduces the leakage current of the chip which makes power gated static random access memories (SRAM) circuits for implementing sleep mode, which is considered an efficient power management technique. In [35], the authors propose a quasi-powergating approach in order to reduce leakage power dissipation on SRAM banks. Other applications of power gating are observed in network-on-chip(s) (NoCs) [36] and Non-Volatile (NV) memory technologies [37] where the authors proposed a power gated 1 Mb NV embedded memory to optimize the trade-off between macro size and its operational power.…”

Section: Related Workmentioning

confidence: 99%

VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design

Goswami¹,

Mondal²,

Das³

et al. 2022

Preprint

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Dynamic Random Access Memory (DRAM) is the de-facto choice for main memory devices due to its cost-effectiveness. It offers a larger capacity and higher bandwidth compared to SRAM but is slower than the latter. With each passing generation, DRAMs are becoming denser. One of its side-effects is the deviation of nominal parameters: process, voltage, and temperature. DRAMs are often considered as the bottleneck of the system as it trades off performance with capacity. With such inherent limitations, further deviation from nominal specifications is undesired. In this paper, we investigate the impact of variations in conventional DRAM devices on the aspects of performance, reliability, and energy requirements. Based on this study, we model a variation-aware framework, called VAR-DRAM, targeted for modern-day DRAM devices. It provides enhanced power management by taking variations into account. VAR-DRAM ensures faster execution of programs as it internally remaps data from variation affected cells to normal cells and also ensures data preservation. On extensive experimentation, we find that VAR-DRAM achieves peak energy savings of up to 48.8% with an average of 29.54% on DDR4 memories while improving the access latency of the DRAM compared to a variation affected device by 7.4%. Keywords DRAM • Process Variation • Power ManagementThe classic monolithic design of a typical DRAM has been enhanced to accommodate better performance in minimal power requirements. A modern-day DRAM device is organized into ranks and banks. Although this memory layer

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“…Power Gating (PG) technology has been widely used to save SRAM power consumption [26,27]. In this specific case of SRAM-based WB, we propose the following design according to our previous simulation results.…”

Section: Power Gated Wbmentioning

confidence: 99%

A STT-RAM-based low-power hybrid register file for GPGPUs

Chen

Sun

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Recently, general-purpose graphics processing units (GPGPUs) have been widely used to accelerate computing in various applications. To store the contexts of thousands of concurrent threads on a GPU, a large static random-access memory (SRAM)-based register file is employed. Due to high leakage power of SRAM, the register file consumes 20% to 40% of the total GPU power consumption. Thus, hybrid memory system, which combines SRAM and the emerging non-volatile memory (NVM), has been employed for register file design on GPUs. Although it has shown strong potential to alleviate the power issue of GPUs, existing hybrid memory solutions might not exploit the intrinsic feature of GPU register file. By leveraging the warp schedule on GPU, this paper proposes a hybrid register architecture which consists of a NVM-based register file and mixed SRAM-based write buffers with a warp-aware write back strategy. Simulation results show that our design can eliminate 64% of write accesses to NVM and reduce power of register file by 66% on average, with only 4.2% performance degradation. After we apply the power gating technique, the register power is further reduced to 25% of SRAM counterpart on average.

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A quasi-power-gated low-leakage stable SRAM cell

Cited by 12 publications

References 7 publications

Multi retention level STT-RAM cache designs with a dynamic refresh scheme

Multi retention level STT-RAM cache designs with a dynamic refresh scheme

VAR-DRAM: Variation-Aware Framework for Efficient Dynamic Random Access Memory Design

A STT-RAM-based low-power hybrid register file for GPGPUs

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