A quasi-passive CMOS pipeline D/A converter

Wang, F.-J.; Temes, Gábor C.; Law, S.

doi:10.1109/cicc.1988.20890

Cited by 3 publications

(5 citation statements)

References 9 publications

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“…It can be seen in (19) that parasitic capacitance Cpar narrows down the range of unit cap Cu. Figure 9.…”

Section: Capacitance Parasitic Effectsmentioning

confidence: 99%

“…Due to imperfections of the transistor switches (Roff / Ron resistances) the leakage and incomplete settling in the capacitor array result in voltage errors which degrade DAC linearity [19]. Firstly the upper bound of on-resistance of switch is estimated.…”

Section: Settling Timementioning

confidence: 99%

“…17 shows design area W-Cu of 12-bit (6-6 segmentation) and 13-bit (7-6 segmentation) SC DACs for clock frequency fs = 5 GHz. The solid lines which consist of SSN (22), settling time (19) and mismatch (12) are upper/lower bounds of 12-bit SC DACs. The mismatch coefficients in (12) are taken from 65 nm CMOS process.…”

Section: Design Area W-cumentioning

confidence: 99%

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Design and analysis of high-speed split-segmented switched-capacitor DACs

Duong

Bhide

Alvandpour

2017

Analog Integr Circ Sig Process

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In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise (SSN) are mathematically analyzed and modelled. The design area W-Cu is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (W, Cu) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition (DS) technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range (SFDR) within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio (PSRR) in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.Index Terms-high-speed DACs, SC DACs, 12-bit splitsegmented DACs, linear output driver, wideband wireless communications. Clk-Clk+ Out+ Decoder

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“…It can be seen in (19) that parasitic capacitance Cpar narrows down the range of unit cap Cu. Figure 9.…”

Section: Capacitance Parasitic Effectsmentioning

confidence: 99%

Section: Settling Timementioning

confidence: 99%

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Design and analysis of high-speed split-segmented switched-capacitor DACs

Duong

Bhide

Alvandpour

2017

Analog Integr Circ Sig Process

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“…Through pipelining, the number of bits per stage can be reduced. This approach partitions the number of bits to be resolved over successive pipeline stages [20]- [23]. Because the internal DAC of an oversampled DAC is o u t s i d e the feedback loop, as opposed to the internal DAC in an oversampled ADC which is i n s i d e t h e feedback loop, the latency or delay introduced by pipelining does not cause any stability problem.…”

Section: A R C H I T E C T U R Ementioning

confidence: 99%

“…If the internal DAC is realized using switched-capacitor implementation the overall linearity is limited by nonideal effects of the subblocks from each stage [20]. These nonidealities stemmed from errors due to nonideal op amps, switches, and capacitors.…”

Section: Limitations Of Switched-capacitor Implementationmentioning

confidence: 99%

Pipelined multibit oversampled digital-to-analog converters with capacitor averaging

Leung

1992

Analog Integr Circ Sig Process

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A combination of pipelined architecture and dynamic element matching technique is applied to multibit oversampled D/A (digital to analog) converters. The approach translates the harmonic distortion components of the nonideal internal DAC (digital-to-analog converter) of the oversampled DAC to high-frequency components, which can then be filtered out by the analog low-pass filter for anti-imaging. Computer simulations have confirmed that with this approach a third-order oversampled DAC employing a 3-bit quantizer, a 3-bit pipelined internal DAC with a random mismatch of 0.1%, can achieve a 94-dB dynamic range with an oversampling ratio of 64 while eliminating the harmonic distortion.

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Novel pipeline data converters

Temes¹,

Wang²,

Watanabe³

1988., IEEE International Symposium on Circuits and Systems

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A quasi-passive CMOS pipeline D/A converter

Cited by 3 publications

References 9 publications

Design and analysis of high-speed split-segmented switched-capacitor DACs

Design and analysis of high-speed split-segmented switched-capacitor DACs

Pipelined multibit oversampled digital-to-analog converters with capacitor averaging

Novel pipeline data converters

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