Design and analysis of high-speed split-segmented switched-capacitor DACs

Abstract

In order to achieve high speed and high resolution for switched-capacitor (SC) digital-to-analog converters (DACs), an architecture of split-segmented SC DAC is proposed. The detailed design considerations of kT/C noise, capacitor mismatch, settling time and simultaneous switching noise (SSN) are mathematically analyzed and modelled. The design area W-Cu is defined based on that analysis. It is used not only to identify the maximum speed and resolution but also to find the design point (W, Cu) for certain speed and resolution of SC DAC topology. The segmentation effects are also considered. An implementation example of this type of DACs is a 12-bit 6-6 split-segmented SC DAC designed in 65 nm CMOS. The linear open-loop output driver utilizing derivation superposition (DS) technique for nonlinear cancellation is used to drive off-chip load for the SC array without compromising its performance. The measured results show that the SC DAC achieves a 44 dB spurious free dynamic range (SFDR) within a 1 GHz bandwidth of input signal at 5 GS/s while consuming 50 mW from 1 V digital and 1.2 V analog supplies. The overall performance that was achieved from measurement is poorer than expected due to lower power supply rejection ratio (PSRR) in fabricated chip. This DAC can be used in transmitter baseband for wideband wireless communications.Index Terms-high-speed DACs, SC DACs, 12-bit splitsegmented DACs, linear output driver, wideband wireless communications. Clk-Clk+ Out+ Decoder

Studies on the performance bounds and design of current-steering DACs

“…2.12. Note that the DACs achieve an SFDR ≥ 40 dBc up to 10 GHz, except for [35]. Thereafter, the SFDR drops rapidly, reaching up to 25 dBc [40], which is attributed due to the mid-and low-resolution DACs implementations at f s > 10 GHz as well as fast linearity degradation with larger BW .…”

“…A conventional closed-loop driver with negative feedback to mitigate for the non-linearity in the driver results in limited bandwidth. Alternatively, open-loop solutions have also been proposed at the cost of added complexity to compensate for the output driver's nonlinear response [34], [35]. Common capacitive DAC implementations for the chargeredistribution and switch-capacitor are presented in Fig.…”

“…A comparison of high-speed DACs implemented in CMOS, BiCMOS and HBT technologies are presented next. DACs report an f s below 1 GHz [34], [36], except in [35], which reaches a BW of 2.5 GHz. Moreover, the sub-nm CMOS CS DACs report an f s in the GHzrange, reaching up to 100 GHz in [40].…”