A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1<sup>st</sup> speculative tap

Jeon, Gyunam; Kim, Yong-Bin

doi:10.1109/isocc.2017.8368875

Cited by 2 publications

(2 citation statements)

References 3 publications

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“…A typical DFE has summers depending on the number of interleaves (shown as a gray line in Fig. 2) [4,18,19,20,23,24,25]. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer.…”

Section: Proposed Dfe Architecturementioning

confidence: 99%

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Kang

Song

2021

IEICE Electron. Express

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This paper describes quad-rate 1-FIR 2-IIR decision feedback equalizer (DFE) with summer reduction technique for high-speed serial communication in a 65nm CMOS technology. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer. Therefore, the proposed DFE reduces power consumption significantly because summer dissipates a lot of power. The DFE that is verified by pre-layout simulations achieved 0.69 unitinterval (UI) eye-opening. The proposed DFE that is designed with a 65-nm technology operates at 28Gb/s and occupies 0.023mm 2 . Finally, the power efficiency of the proposed DFE is 0.88-pJ/bit.

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Section: Proposed Dfe Architecturementioning

confidence: 99%

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

Kang

Song

2021

IEICE Electron. Express

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“…Due to the existence of RC time constant formed by load resistance and parasitic capacitance, the resistively loaded CML summer has high DC power dissipation [20]. The switched-capacitor summer requires no DC power, but it needs more clock signals [21,22].…”

Section: Introductionmentioning

confidence: 99%

6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

Sun

Zhang

Yang

2022

IEICE Electron. Express

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This paper presents a wide rate range receiver including adaptive continuous time linear equalizer (CTLE) and loop-unrolled half rate decision feedback equalizer (DFE). A hybrid filter is adopted to expand the rate range of adaptive CTLE with spectrum balancing technology. The current-integrating summer is introduced to reduce the power of half-rate loop-unrolled DFE. The post-simulation is carried out by 0.18 μm CMOS TSMC technology and the results show that the rate range of adaptive CTLE can reach to 6.25-10 Gb/s. When the 10 Gb/s PRBS7 signal is transmitted through the 18-inch FR4 backplane with 15.451 dB loss at Nyquist frequency, the eye diagram is obviously open and its horizontal opening is about 0.9 UI.

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A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1^st speculative tap

Cited by 2 publications

References 3 publications

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

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A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap

Cited by 2 publications

References 3 publications

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process

6.25-10Gb/s adaptive CTLE with spectrum balancing and loop-unrolled half-rate DFE in TSMC 0.18µm CMOS

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A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1^st speculative tap