A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor

Wang, Xu; Gao, Gan; Manzano, Joseph; Fan, Dongrui; Guo, Shuxu

doi:10.1109/icpads.2008.18

Cited by 13 publications

(6 citation statements)

References 17 publications

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“…Such memory connection can utilize the regular router design and interconnections effectively. Similar designs can be found in [21] and [22]. There could be different physical implementations regarding the memory type, connectivity, and memory hierarchy design.…”

Section: A Cluster-based Processor Organizationmentioning

confidence: 93%

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

Liu

Zhang

Wang

et al. 2016

IEEE Trans. VLSI Syst.

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As transistor density continues to increase with the advent of nanotechnology, reliability issues raised by more frequently appeared soft errors are becoming even more critical to the next-generation multiprocessor systems. In this paper, we present a systematic approach to address the soft-error problem in multiprocessor system-on-chip with the consideration of system performance optimization. To guarantee the system correctness, a hardware-software collaborated approach is proposed to protect the processors from soft errors. Tiny hardware sensors are embedded in the processor cores to detect the soft errors, and the software-based rollback scheduling mechanisms are applied for error recovery. The protection costs on hardware duplication and software redundancy are effectively reduced. To optimize the system performance, a distributed control system is built on top of the on-chip communication network and collaboratively manages the entire chip for application execution. With the cluster-based task migration techniques, an efficient runtime task remapping and rescheduling algorithm is proposed to further mitigate the overheads induced by soft-error protection and to minimize the total performance degradation. The distributed control strategy makes the system more adaptable and flexible to the development of the next-generation hardware and software with larger scales. Extensive performance evaluations using SystemC-based cycleaccurate simulations on a set of real-world applications show that our approach has on average 49% performance improvement and 79.6% energy consumption reduction compared with the related state-of-the-art techniques, and hardware synthesis results show that our approach only introduces 2.9% chip area overheads.

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Section: A Cluster-based Processor Organizationmentioning

confidence: 93%

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

Liu

Zhang

Wang

et al. 2016

IEEE Trans. VLSI Syst.

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“…• Latency tolerance [7]. Since there may exist intensive contention on on-chip network and memory controller, latency to L2 cache will possibly become primary obstacle to achieve decent performance.…”

Section: Godson-t Many-core Architecturementioning

confidence: 99%

Preliminary Investigation of Accelerating Molecular Dynamics Simulation on Godson-T Many-Core Processor

Liu

Tan

Kalia

et al. 2011

Euro-Par 2010 Parallel Processing Workshops

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Molecular dynamics (MD) simulation is widely used in computational science, however, its irregular memory-access pattern imposes great difficulty on performance optimization. This paper presents a joint application/architecture study to accelerate MD on an emerging unconventional computing platformGodson-T many-core architecture. We propose three incremental optimizations: (1) a divide-andconquer algorithm adaptive to on-chip memory; (2) a novel data-layout to re-organize linked-list cell data structures to improve data locality; (3) an on-chip locality-aware parallel algorithm to enhance data reuse. Experiments on an event-driven, cycle-accurate Godson-T simulator achieve excellent speedup of 62 on 64 cores.

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“…With the arrival of many-core architectures, the variance of processors increases by another order of magnitude. This variance increases also the need for high-level language virtual machines (VMs) to abstract from variations introduced by differences among many-core architectures [19,35,43,44]. We are concerned with processors having multiple cores, using non-uniform memory access architectures, and explicit mechanisms for inter-core communication.…”

Section: Motivationmentioning

confidence: 99%

Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models

Marr

Haupt

Timbermont

et al. 2010

Electron. Proc. Theor. Comput. Sci.

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The upcoming many-core architectures require software developers to exploit concurrency to utilize available computational power. Today's high-level language virtual machines (VMs), which are a cornerstone of software development, do not provide sufficient abstraction for concurrency concepts. We analyze concrete and abstract concurrency models and identify the challenges they impose for VMs. To provide sufficient concurrency support in VMs, we propose to integrate concurrency operations into VM instruction sets. Since there will always be VMs optimized for special purposes, our goal is to develop a methodology to design instruction sets with concurrency support. Therefore, we also propose a list of trade-offs that have to be investigated to advise the design of such instruction sets. As a first experiment, we implemented one instruction set extension for shared memory and one for non-shared memory concurrency. From our experimental results, we derived a list of requirements for a full-grown experimental environment for further research

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A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor

Cited by 13 publications

References 17 publications

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

Preliminary Investigation of Accelerating Molecular Dynamics Simulation on Godson-T Many-Core Processor

Virtual Machine Support for Many-Core Architectures: Decoupling Abstract from Concrete Concurrency Models

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