A Quality-Driven Design Approach for NoCs

Bourduas, S.; Chenard, J.-S.; Žilić, Željko

doi:10.1109/mdt.2008.124

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…As a result, software debugging can be accelerated by an order of magnitude over uncompressed trace extraction. In future, we plan to combine our software debugging efforts with assertion-based debugging [3], as part of a testing, monitoring, and debugging infrastructure for SoCs and networks-on-chip [4].…”

Section: Discussionmentioning

confidence: 99%

Real-time address trace compression for emulated and real system-on-chip processor core debugging

Mihajlović

Žilić

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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In the multicore era, capturing execution traces of processors is indispensable to debugging complex software. The inability to transfer vast amounts of trace data off-chip without significant slow-down has impeded the debugging of such software, in both pre-silicon emulation and in real designs. We consider on-chip trace compression performed in hardware to reduce data volume, using techniques that exploit inherent higher-order redundancy in address trace data. While hardware trace compression is often restricted to poor or moderate performance due to area and memory constraints, we present a parameterizable scheme that leverages the resources already found on existing platforms. Harnessing resources such as existing trace buffers on CPUs, and unused embedded memory on FPGA emulation platforms, our trace compression scheme requires only a small additional hardware area to achieve superior compression ratios.

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Section: Discussionmentioning

confidence: 99%

Real-time address trace compression for emulated and real system-on-chip processor core debugging

Mihajlović

Žilić

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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“…When added to the traditional design flow, ESL can be used in conjunction with RTL implementation in order to drive cost-aware architectural exploration [3]. That is, the properties of the RTL implementation can be used to develop cost models to drive the design space exploration using approximations rather than having to implement each design instance in RTL [4].…”

Section: Introductionmentioning

confidence: 99%

A comparison of two multistage ring architectures for NoC using high-level simulation models

Bourduas

Žilić

2008

2008 1st Microsystems and Nanoelectronics Research Conference

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This paper uses high-level simulation models written in SystemC to compare the performance characteristics of two wormhole-routed multistage ring architectures: a hierarchical ring and a two-dimensional hyper ring. The hierarchical ring architecture has a single global ring, which limits its bisection bandwidth. The hyper ring is presented as an improvement over the hierarchical ring, whereby a second global ring is used to double the bisection bandwidth. Furthermore, a "fat" variant of each architecture is considered, which use bidirectional global rings to increase the bisection bandwidth of the original architectures.

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Modeling and evaluation of ring-based interconnects for Network-on-Chip

Bourduas¹,

Žilić²

2011

Journal of Systems Architecture

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A Quality-Driven Design Approach for NoCs

Cited by 4 publications

References 10 publications

Real-time address trace compression for emulated and real system-on-chip processor core debugging

Real-time address trace compression for emulated and real system-on-chip processor core debugging

A comparison of two multistage ring architectures for NoC using high-level simulation models

Modeling and evaluation of ring-based interconnects for Network-on-Chip

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