A quadrature bandpass ΣΔ modulator for digital radio

Jantzi, S.; Martin, K.; Sedra, A.S.

doi:10.1109/isscc.1997.585339

Cited by 19 publications

(11 citation statements)

References 4 publications

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“…A complex bandpass ΔΣAD modulator gains its advantage by implementing the poles and zeros of its loop filter without conjugates, which effectively cancels the leakeage in the image band for a complex single-side band signal. Figure 1 shows the signal-flow-graph (SFG) of complex bandpass ΔΣAD modulator [2], [3], and Fig. 2 shows its simplified structure, which is composed of a complex bandpass filter, two internal quantizers(ADCs) and two DACs.…”

Section: Complex Bandpass δσAd Modulatormentioning

confidence: 99%

Cross-Noise-Coupled Architecture of Complex Bandpass .DELTA..SIGMA.AD Modulator

San

Kobayashi

2009

IEICE Trans. Fundamentals

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Complex bandpass ΔΣAD modulators can provide superior performance to a pair of real bandpass ΔΣAD modulators of the same order. They process just input I and Q signals, not image signals, and AD conversion can be realized with low power dissipation, so that they are desirable for such low-IF receiver applications. This paper proposes a new architecture for complex bandpass ΔΣAD modulators with cross-noisecoupled topology, which effectively raises the order of the complex modulator and achieves higher SQNDR (Signal to Quantization Noise and Distortion Ratio) with low power dissipation. By providing the cross-coupled quantization noise injection to internal I and Q paths, noise coupling between two quantizers can be realized in complex form, which enhances the order of noise shaping in complex domain, and provides a higher-order NTF using a lower-order loop filter in the complex ΔΣAD modulator. Proposed higher-order modulator can be realized just by adding some passive capacitors and switches, the additional integrator circuit composed of an operational amplifier is not necessary, and the performance of the complex modulator can be effectively raised without more power dissipation. We have performed simulation with MATLAB to verify the effectiveness of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of higher-order enhancement, and improve SQNDR of the complex bandpass ΔΣAD modulator.

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Section: Complex Bandpass δσAd Modulatormentioning

confidence: 99%

Cross-Noise-Coupled Architecture of Complex Bandpass .DELTA..SIGMA.AD Modulator

San

Kobayashi

2009

IEICE Trans. Fundamentals

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“…Complex poles can be 0-7803-9735-5/06/$20.00 ©2006 IEEE implemented either with real integrators [6], or with a cascade of unit delay-cell architecture [7], which is shown in Fig.2(a). In our modulator design, we choose the delay-cell architecture since it operates fast and has simple coefficient values.…”

Section: Complex Bandpass Azad Modulator Topologymentioning

confidence: 99%

A Multibit Complex Bandpass AZAD Modulator with I, Q Dynamic Matching and DWA Algorithm

San

Jingu

Wada

et al. 2006

2006 IEEE Asian Solid-State Circuits Conference

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A second-order multi-bit switched-capacitor complex bandpass AEAD modulator has been designed and fabricated for application to low-IF receivers in wireless communication systems such as Bluetooth and WLAN. We propose a new structure of a complex bandpass filter in forward path with I, Q dynamic matching which is equivalent to the conventional one but it can be divided into two separate parts. As a result, the AY, modulator which constituted with our proposed complex filter can be completely divided into two separate parts too, and there are not any signal line crossing between the upper and lower paths by a complex filter and feedback from DACs. Therefore, the layout design of the modulator can be greatly simplified. Nine-level two quantizers and four DACs are used in the modulator for lower power implementation and higher SNDR, but the nonlinearities of DACs are not noise-shaped and the SNDR of the AZ\ ADC degrades. We have employed a new complex bandpass Data-Weighted Averaging (DWA) algorithm to suppress nonlinearity effects of multibit DACs in complex form to achieve high accuracy; it can be realized just by adding simple digital circuitry. Implemented in a 0.18-,um CMOS process and at 2.8V supply, the modulator achieves a measured peak signalto-noise-and-distortion (SNDR) of 64.5dB at 2OMS/s with a signal bandwidth of 78kHz while dissipating 28.4mW and occupying a chip area of 1.82mm2.

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“…In the recent era, the interesting for high-speed high-resolution mixed-signal ICs has been growing due to the diffusion of applications based on digital signal processing, including audio and video signal processing, as well as over sampled sigma-delta Analog-Digital (A/D) and Digital-Analog (D/A) conversion [1][2][3][4][5] . In these ICs, analog and digital circuits are implemented on the same silicon substrate and the resolution of the analog circuitry is severely restricted by the amount of switching noise generated by the digital blocks [6][7][8] .…”

Section: Introductionmentioning

confidence: 99%

Source Couple Logic (SCL): Theory and Physical Design

Azaga¹,

Othman²

2008

American J. of Engineering and Applied Sciences

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This study describes and presents the analysis for the Source-Coupled Logic (SCL) inverter as will as the effect of submicron layout parasitics. The SCL inverter circuit model and its operation is defined. The analysis for the SCL is carried from the point of view of input/output voltage characteristics and the effect of noise margin. The inverter gate delay model is described and the effect of biasing current on the delay is shown. The result shows that, the delay of the SCL inverter is decreased as biasing current increase. The simulation is done based on the 0.18 Âµ Silterra PDK. Different layouts for SCL inverter have been investigated for its effect on output voltage swing, switching noise and the area. The results show an important effect on the SCL output signals. Post-Simulation was carried out on all proposed layouts using HSPICE and using 0.35 µ MIMOS Berhad PDK. The layout was done using Virtuous from Cadence where as the extraction done using Mentor Graphic-Caliber Interactive tool

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A quadrature bandpass ΣΔ modulator for digital radio

Cited by 19 publications

References 4 publications

Cross-Noise-Coupled Architecture of Complex Bandpass .DELTA..SIGMA.AD Modulator

Cross-Noise-Coupled Architecture of Complex Bandpass .DELTA..SIGMA.AD Modulator

A Multibit Complex Bandpass AZAD Modulator with I, Q Dynamic Matching and DWA Algorithm

Source Couple Logic (SCL): Theory and Physical Design

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