A Quad-Band GSM/GPRS/EDGE SoC in 65 nm CMOS

Darabi, Hooman; Chang, P.J.; Jensen, Henrik Toft; Zolfaghari, A.; Lettieri, P.; Leete, J.; Mohammadi, Behnam; Chiu, J.; Li, Qiang; Chen, Shr-Lung; Zhou, Zhimin; Vadipour, M.; Chen, C; Chang, Yuyu; Mirzaei, Ahmad; Yazdi, A.; Nariman, Med; Hadji-Abdolhamid, Amir; Chang, E.; Zhao, Bin; Juan, K.; Suri, P; Guan, Claire; Serrano, L.; Leung, J.; Shin, Ji-Hyun; Kim, J; Tran, H.; Kilcoyne, P.; Vinh, Huynh Le; Raith, E.; Koscal, M; Hukkoo, Ajat; Hayek, C.; Rakhshani, V.; Wilcoxson, C.; Rofougaran, M.; Rofougaran, A.

doi:10.1109/jssc.2011.2109432

Cited by 31 publications

(11 citation statements)

References 12 publications

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“…Since this work is the first reported E-EDGE solution, comparison is only possible for the voice sensitivity (testcase 1). The sensitivity performance of our E-EDGE solution lies in a competitive range and shows better sensitivity than [20], [1], [21]. Our system shows a sensitivity of 1.2 dB below the transceiver of [22], which reports a sensitivity of 113 dBm (Class II RBER) and is based on a noise figure of 2.4 dB, while our RF-IC has a noise figure of 4 dB [17] including front-end insertion loss.…”

Section: Performance Measurement Resultsmentioning

confidence: 99%

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity

Kroll

Zwicky

Weber

et al. 2015

IEEE J. Solid-State Circuits

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In this paper, a baseband ASIC which supports receive diversity and soft-output Viterbi equalization for enhanced 2G networks is presented. It includes a transmitter and receiver with a symbol detector and a decoder with a dedicated incremental redundancy implementation, as well as the necessary control capability to autonomously communicate with the RF-IC. The ASIC is connected to an RF-IC to build a complete Evolved EDGE transceiver system. The transceiver system reaches a measured sensitivity close to 112 dBm for single-antenna GSM voice channels and achieves the reference interference performance for adjacent channels 11.4 dB above 3GPP requirements. It is the first reported solution which fulfills the most demanding 3GPP Downlink Advanced Receive Performance Phase 2 testcases specified for Rx-diversity. The ASIC occupies 6 mm in 130 nm CMOS with a power consumption between 3.9 and 14 mW.Index Terms-Baseband ASIC, enhanced 2G networks, evolved EDGE (E-EDGE), evolved EDGE testbed, GSM/EDGE, hybrid ARQ, incremental redundancy, interference cancellation, internet of things (IoT), machine-to-machine (M2M), Rx diversity, space-time processing.

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Section: Performance Measurement Resultsmentioning

confidence: 99%

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity

Kroll

Zwicky

Weber

et al. 2015

IEEE J. Solid-State Circuits

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“…For digital baseband processing in the PHY a DSP with a number of accelerators is employed. The latest publications on GSM/EDGE transceivers tend towards SoC implementations including RF, digital baseband, application CPU, and peripherals [5,6]. Commercially available products (e.g.…”

Section: Iotmentioning

confidence: 99%

“…However, power consumption is high. Indeed [6] claims to draw 232 mW and [5] 310 mW in transmit mode. In receive mode [5] gets as low as 176 mW.…”

Section: Iotmentioning

confidence: 99%

On the Mapping of Incremental Redundancy into a Physical Layer ASIC

Weber

Kroll

Benkeser

et al. 2014

J Sign Process Syst

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Incremental Redundancy (IR) was introduced in GSM/EDGE and later adopted in Evolved EDGE in order to keep the throughput at an acceptable level. Legacy 2G networks with their ubiquitous coverage are apt to provide a fallback solution for the latest LTE networks. On the other hand, they provide a reliable data link for emerging M2M or IoT applications. IR data processing and controlling is specified in several layers of the GSM/EDGE protocol stack. In many state-of-the-art designs this leads to decentralized data processing, and thus to costly data movements between memories and hardware accelerators. This is prohibitive for emerging M2M designs, which demand lowest possible hardware resources. In this work, IR is implemented as part of a dedicated hardware baseband signal processing unit in order to unburden higher layer processing units from IR, reduce area, power consumption, and costs. The open source baseband framework MatPHY is extended for packet switched operation to facilitate the development of efficient IR hardware architectures. With the design parameters obtained from performance evaluations computed with MatPHY an IR architecture in a 130 nm CMOS technology B. Weber ( ) •

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“…However, under process, voltage, and temperature (PVT) variations, mismatch between the digital filter and the analog PLL will lead to degraded modulation accuracy. Hence, several techniques have been proposed to tackle this digital-analog mismatch [7]- [10].…”

Section: Introductionmentioning

confidence: 99%

“…In [7], a scalable charge pump current was employed to compensate the loop gain error. Based on an over-damped, second-order loop filter PLL structure approximation, the PLL bandwidth was proportional to the product of loop resistance, and VCO sensitivity [18].…”

Section: Introductionmentioning

confidence: 99%

A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration

Huang

Chen

Guo

et al. 2015

IEEE Trans. Circuits Syst. I

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A delta-sigma phase locked loop (PLL) transmitter with an efficient modulation bandwidth calibration technique is proposed in this paper. With the proposed technique, the digital-analog mismatch between digital pre-emphasis filter and PLL is calibrated. The loop filter variation is tracked in the first place, and then the variation of the loop gain is calibrated by sensing the magnitude differences of the modulator between DC and ten times of the loop bandwidth. The proposed transmitter has been implemented in 0.18-CMOS technology for GSM/GPRS application. Measurement results show that the maximum RMS phase error of the proposed transmitter is 0.8 . In addition, the measured calibration accuracies for and loop gain variations are 0.5% and 0.8%, respectively. By reusing the PLL locking time, 18-calibration time is achieved. Moreover, most parts of the calibration circuitries can be shared with the receiver chain, reducing the circuit complexity overhead. Index Terms-Delta-sigma phase locked loop (PLL), modulation bandwidth calibration, transmitters.Manuscript

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A Quad-Band GSM/GPRS/EDGE SoC in 65 nm CMOS

Cited by 31 publications

References 12 publications

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity

On the Mapping of Incremental Redundancy into a Physical Layer ASIC

A CMOS Delta-Sigma PLL Transmitter with Efficient Modulation Bandwidth Calibration

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