A pythonic approach for rapid hardware prototyping and instrumentation

Clow, John E.; Tzimpragos, Georgios; Dangwal, Deeksha; Guo, Sammy; McMahan, Joseph; Sherwood, Timothy

doi:10.23919/fpl.2017.8056860

Cited by 39 publications

(19 citation statements)

References 10 publications

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“…Looking ahead, we see that tools such as this hold significant promise in enabling more collaborative and community-driven efforts that can make our best thinking on the future of architecture more readily and easily accessible to all who are interested. Furthermore, although Charm focuses on facilitating models analysis, we believe that by combining Charm with other hardware design toolsets (e.g., PyRTL [17]), we can automate the process of developing actual hardware designs directly from performance studies (e.g., via templates).…”

Section: Resultsmentioning

confidence: 99%

“…We release Charm as an open source tool on GitHub 1 to serve as a framework the architecture community can utilize to define and share analytical models. We also provide a wide collection of established architecture models from literature for quick use/reference, including the dark silicon model [24], a resource overhead model for implementing magic state distillation on surface code [11], mechanistic CPU models [12,26], a TCAM power model [2], the LogCA model for accelerators [5], the adder/multiplier models from PyRTL [16], a widely used CNN roofline model [73], dynamic power and area models for NoC [37], specifications of Xilinx 7-series FPGA [71], and the extended Hill-Marty model [21].…”

mentioning

confidence: 99%

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Language Support for Navigating Architecture Design in Closed Form

Cui

Tzimpragos

Tao

et al. 2019

J. Emerg. Technol. Comput. Syst.

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As computer architecture continues to expand beyond software-agnostic microarchitecture to specialized and heterogeneous logic or even radically different emerging computing models (e.g., quantum cores, DNA storage units), detailed cycle-level simulation is no longer presupposed. Exploring designs under such complex interacting relationships (e.g., performance, energy, thermal, frequency) calls for a more integrative but higher-level approach. We propose Charm, a modeling language supporting closed-form high-level architecture modeling. Charm enables mathematical representations of mutually dependent architectural relationships to be specified, composed, checked, evaluated, reused, and shared. The language is interpreted through a combination of automatic symbolic evaluation, scalable graph transformation, and efficient compiler techniques, generating executable DAGs and optimized analysis procedures. Charm also exploits the advancements in satisfiability modulo theory solvers to automatically search the design space to help architects explore multiple design knobs simultaneously (e.g., different CNN tiling configurations). Through two case studies, we demonstrate that Charm allows one to define high-level architecture models in a clean and concise format, maximize reusability and shareability, capture unreasonable assumptions, and significantly ease design space exploration at a high level.

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Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

Language Support for Navigating Architecture Design in Closed Form

Cui

Tzimpragos

Tao

et al. 2019

J. Emerg. Technol. Comput. Syst.

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“…1. Readers could refer to [3] for detailed explanation. In PyRTL, all the W ireV ector and LogicN et objects are organized in a Block object.…”

Section: Background a Overview Of Pyrtl And Its Ir Formatmentioning

confidence: 99%

“…This growing complexity has led to a design productivity crisis. Some novel hardware description languages (HDLs), which are usually embedded in some modern programming languages as domain-specific languages for hardware (HDSLs), are developed to improve design productivity, such as Chisel [2] on Scala, PyRTL [3] and PyMTL [4] on Python, and CλaSH [5] on Haskell. HDSLs are also a kind of hardware construction language (HCL), which means the designs are elaboratedthrough-execution.…”

Section: Introductionmentioning

confidence: 99%

Symbolic Simulation Enhanced Coverage-Directed Fuzz Testing of RTL Design

Zou

Luo

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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With the ending of Moore's Law and Dennard scaling, modern System-on-a-Chip (SoC) trends to incorporate a large and growing number of specialized modules for specific applications. Verification is vital to the RTL design and faces new challenges due to the growing design complexities. In this paper, we proposed a symbolic simulation enhanced coveragedirected dynamic verification technique for RTL designs. We proposed novel Full Multiplexer Toggle Coverage (FMTC) to trace and provide feedback to the verification process. The proposed method is a hybrid between symbolic simulation and mutation based fuzz testing that offsets the disadvantages of both. The achievement of high coverage is obtained by interleaved symbolic simulation and fuzz testing passes. The symbolic simulation pass is used to generate tests that direct the testing to untouched corners. While the mutation based fuzz testing pass is used to leverage test generation tasks and to enable the method to deal with large scale designs. The empirical evaluation of the method shows promising results on archiving high coverage for practical designs.

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“…For the development and verification of a Race Trees design, PyRTL [10], a Python embedded hardware design language, is used. The fact that both scikit-learn and PyRTL are built around Python makes their integration easier and assists verification.…”

Section: Evaluation Of Correctnessmentioning

confidence: 99%

Boosted Race Trees for Low Energy Classification

Tzimpragos

Madhavan

Vasudevan

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

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When extremely low-energy processing is required, the choice of data representation makes a tremendous difference. Each representation (e.g. frequency domain, residue coded, logscale) comes with a unique set of trade-offs-some operations are easier in that domain while others are harder. We demonstrate that race logic, in which temporally coded signals are getting processed in a dataflow fashion, provides interesting new capabilities for in-sensor processing applications. Specifically, with an extended set of race logic operations, we show that tree-based classifiers can be naturally encoded, and that common classification tasks can be implemented efficiently as a programmable accelerator in this class of logic. To verify this hypothesis, we design several race logic implementations of ensemble learners, compare them against state-of-the-art classifiers, and conduct an architectural design space exploration. Our proof-of-concept architecture, consisting of 1,000 reconfigurable Race Trees of depth 6, will process 15.2M frames/s, dissipating 613mW in 14nm CMOS. CCS Concepts • Computer systems organization → Architectures; • Computing methodologies → Machine learning; • Hardware → Hardware accelerators.

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A pythonic approach for rapid hardware prototyping and instrumentation

Cited by 39 publications

References 10 publications

Language Support for Navigating Architecture Design in Closed Form

Language Support for Navigating Architecture Design in Closed Form

Symbolic Simulation Enhanced Coverage-Directed Fuzz Testing of RTL Design

Boosted Race Trees for Low Energy Classification

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