A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers

Abstract

Abstract-A 1-Gb/s 0.18-µm CMOS serial-link transceiver using multilevel pulse-width and pulse-amplitude modulation (PWAM) signaling and a pre-emphasis technique is presented. Based on the PWAM technique, the transmit signaling is implemented to effectively push high data rates through bandwidthlimited channels. The clock is implicitly embedded in the 4-bit data stream, and the associated overhead needed in the clock-and-data recovery circuitry can be mitigated. In addition, the pin count can be reduced by transferring the data channels and the clock channel over a single transmitted channel. The recovered clock has an rms jitter of 5.9 ps at 250 MHz, and the retimed data have an rms jitter of 13.7 ps at 250 Mb/s. The occupied die area is 1.65 × 1.40 mm 2 . The transmitter and receiver power consumption is 86 and 45 mW, respectively.Index Terms-Chip-to-chip communication, clock recovery, intersymbol interference (ISI), pulse-amplitude modulation (PAM), pulse-width modulation (PWM), serial link.

A 12‐Gb/s serial link transceiver using dual‐mode pulse amplitude modulation scheme in a 0.18‐μm CMOS process

“…Pulse-width-amplitude modulation (PWAM), which is a combination of PWM and PAM techniques, can achieve a higher data transfer rate using a simplified scheme and pin-count reduction. 4,5 Data and clock channels are combined in this modulation to create an individual channel and the raw binary data is also coded into pulses with different widths and a periodic rising edge. This allows the clock signal to be recovered by using a simple PLL at the receiver.…”

“…This allows the clock signal to be recovered by using a simple PLL at the receiver. However, in the PWAM modulation technique presented in, 4 the pulse width is smaller than a conventional NRZ data pulse width (T b ) and increases the intersymbol interference. A concept of transferring multiple bits over each symbol is also presented in Mostafa et al 6 and Mostafa et al 7 using time-based serial link architecture.…”

Differential-Time and Pulse-Amplitude Modulation Signaling for Serial Link Transceivers

“…Increasing the number of transmitted bits by using amplitude modulation does not appreciably affect the bandwidth of the transmitted signal, however the total number of transmitted bits in a PAM link is restricted because of reduced voltage supply with technology scaling. PAM and pulse-width modulation (PWM) techniques have been combined such as in [4][5], allowing an increase in the total number of transmitted bits by changing both the pulse amplitude and the pulse width according to the input bits. A drawback in such links is that the clock signal is transmitted on a different transmission channel [4][5].…”

“…PAM and pulse-width modulation (PWM) techniques have been combined such as in [4][5], allowing an increase in the total number of transmitted bits by changing both the pulse amplitude and the pulse width according to the input bits. A drawback in such links is that the clock signal is transmitted on a different transmission channel [4][5].…”

Differential Edge Modulation Signaling for Low-Energy, High-Speed Wireline Communication

“…With downward scaled supply voltages, it is challenging to implement higher-order modulation beyond PAM-4. To overcome these limitations and meet the everincreasing bandwidth and energy efficiency requirements, there is a need to explore alternate wireline modulation schemes [6], [7], [8], [9], [10], [11], [12], [13].…”