A prototyping system for high performance communication systems

Dörfel, Matthias; Hofmann, Richard

doi:10.1109/iwrsp.1998.676673

Cited by 10 publications

(2 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Statically configured FPGAs have been used successfully in the rapid prototyping of designs [90,91]. The long fabrication times associated with ASIC design is eliminated.…”

mentioning

confidence: 99%

Computer Aided Engineering for Reconfigurable Computing (CAERC)

Vemuri¹

2001

View full text Add to dashboard Cite

The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Department of Defense, Washington Headquarters Services, Directorate for Information Operations and Reports (0704-0188), 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to any penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. PLEASE DO NOT RETURN YOUR FORM TO THE ABOVE ADDRESS. REPORT DATE (DD-MM-YY)October 2001 2. REPORT TYPE Approved for public release; distribution unlimited. SUPPLEMENTARY NOTES ABSTRACT (Maximum 200 Words)Synthesis and Partitioning for Adaptive and Reconfigurable Computing Systems (SPARCS) is a computer aided engineering environment for reconfigurable computers. SPARCS contains software implementations of a variety of methods and algorithms for various subproblems for automating the task of producing designs for multi-FPGA (Field Programmable Gate Array) based reconfigurable computers. The SPARCS system includes tools for temporal partitioning, spatial partitioning, high-level synthesis, physical design, and arbiter synthesis. This is a comprehensive report on the SPARCS project, describing various techniques developed for solving these problems. In addition, this report contains some experimental results demonstrating the effectiveness of the SPARCS tools. Reconfigurable processors consisting of a sea of uncommitted FPGAs offer the same performance advantages of custom computing while retaining the flexibility of general purpose instruction architectures. In 1996, at the begining of this project, it was predicted that in near future reconfigurable processors can offer lOOx performance improvement over contemporary microprocessors, and 10-100x reduction in power/gate, 20x progress in density, and l,000,000x reduction in reconfiguration time compared to current reconfigurable devices.Unfortunately, state-of-the-art design synthesis methodologies were able to use perhaps 50-75% of the available gates at 30-50% of the maximum clocking rate of single reprogrammable device and were woefully inadequate in synthesizing multi-device systems. In order to deliver the performance expectations of reconfigurable architectures, dramatic improvements in the synthesis tools were necessary in both directions: (1) ability to synthesize to multiple device architectures, and, (2) improvement in utilization and delivered performance of each device. The goal of this project was to develop a coherent design synthesis and partitioning environment for co...

show abstract

“…Statically configured FPGAs have been used successfully in the rapid prototyping of designs [90,91]. The long fabrication times associated with ASIC design is eliminated.…”

mentioning

confidence: 99%

Computer Aided Engineering for Reconfigurable Computing (CAERC)

Vemuri¹

2001

View full text Add to dashboard Cite

show abstract

“…The real implementation may have different architecture from the prototype. Prototyping system proposed by M.Dorfel [3] belongs to this type of platform. The authors use VME-based multiprocessor and PC to perform the software task or software prototyping nodes.…”

Section: Classification Of Reconfigurable Platform By Utilizationmentioning

confidence: 99%

Embedded application prototyping on a communication-restricted reconfigurable platform

Sasongko¹,

Baghdadi²,

Rousseau³

et al.

14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings.

View full text Add to dashboard Cite

As the complexity of SoC is increasing, prototyping becomes more and more suitable than simulation to validate the design. Reconfigurable platform is the solution to attain this prototyping in realistic cost and time. Unfortunately, most of the reconfigurable platforms have fixed communication network. This property becomes a restriction to implement the nowadays applications which have very complex and sophisticated communication network. In this paper, we present a novel approach for embedded application prototyping using reconfigurable platform under communication restriction. The effectiveness of our approach is illustrated through an application example using an ARM Integrator platform

show abstract

Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems

Kaul¹,

Vemuri²

2000

Field-Programmable Custom Computing Technology: Architectures, Tools, and Applications

View full text Add to dashboard Cite

A prototyping system for high performance communication systems

Cited by 10 publications

References 9 publications

Computer Aided Engineering for Reconfigurable Computing (CAERC)

Computer Aided Engineering for Reconfigurable Computing (CAERC)

Embedded application prototyping on a communication-restricted reconfigurable platform

Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems

Contact Info

Product

Resources

About