A Programmable Delay Line for Metastability Characterization in FPGAs

Polzer, Thomas; Huemer, Florian; Steininger, Andreas

doi:10.1109/austrochip.2016.021

Cited by 6 publications

(4 citation statements)

References 8 publications

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“…Speci¯cally in an FPGA environment the carry chain is superior due to (a) its better temporal resolution (recall that the carry logic is speci¯cally optimized for high speed) and (b) its low dependence on the routing (recall that routing has dominant in°uence on the timing in an FPGA). We had already introduced the idea of using a tapped carry chain, 22 but in context with the traditional late transition detector.…”

Section: Control Of the Resolution Timementioning

confidence: 99%

“…Note that for the determination of , which is the most relevant metastability parameter, it is not necessary to know the absolute value of a given t res ; for determining the slope of the graph, just the di®erence between two points, i.e., the step size needs to be precisely known. Still this is a notorious problem in the experimental settings, and even with the digital clock manager a considerable di®erential nonlinearity has been reported, 22 which ultimately limits the precision of the measurement. In general, calibration of the delay elements (step size) is a fundamental prerequisite in all solutions, in order to attain decent accuracy in spite of PVT variations in the delay elements (whichever these may be), as well as in the wiring.…”

Section: Control Of the Resolution Timementioning

confidence: 99%

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An Experimental Study of Metastability-Induced Glitching Behavior

Polzer

Huemer

Steininger

2019

J CIRCUIT SYST COMP

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The increasing number of clock domain crossings in modern systems-on-chip makes the careful consideration of metastability paramount. However, the manifestation of metastability at a flip-flop output is often unduly reduced to late transitions only, while glitches are hardly ever accounted for. In this paper we study the occurrence of glitches resulting from metastability in detail. To this end we propose a measurement circuit whose principle substantially differs from the conventional approach, and by that allows to reliably detect glitches. By means of experimental measurements on an FPGA target we can clearly identify late transitions, single glitches and double glitches as possible manifestations of metastability. Some of these behaviors are unexpected as they do not follow from the traditional modeling theory. We also study the dependence of metastable behavior on supply voltage. Beyond confirming that, as reported in previous literature, the metastable decay constant [Formula: see text] is voltage-dependent, we also produce strong evidence that the relative occurrence of glitches is not voltage-dependent.

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Section: Control Of the Resolution Timementioning

confidence: 99%

Section: Control Of the Resolution Timementioning

confidence: 99%

An Experimental Study of Metastability-Induced Glitching Behavior

Polzer

Huemer

Steininger

2019

J CIRCUIT SYST COMP

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“…Recent studies confirms the vast involvement of routing interconnection network in a variety of applications such as clock tuning [10], Time-to-Digital Converters (TDC) [11], [12], Physical Unclonable Functions (PUF) [13], and True Random Number Generators (TRNG) [14] have shown that full control of the routing path between two given points of the circuit is an essential requirement. It is noted that the placement of circuit elements can be fully controlled by the designer, while routing resources are less controllable.…”

Section: Introductionmentioning

confidence: 97%

Optimum Reconfiguration of Routing Interconnection Network in APSoC Fabrics

Darvishi¹

2020

Preprint

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This paper presents an automated algorithm for optimum configuration of routing interconnection network in Xilinx Zynq-7000 All programmable system-on-chip (APSoC) fabrics. A method to configure circuits with optimum routing resources is presented along with their performance parameters with and without the proposed algorithm. The proposed algorithm enables full control over routing resources for using different interconnection types in order to create routing-based circuit-undertest. The algorithm proposes the routing techniques through the 2-D array of switch matrices inside the interconnection network and automatically identifies the involved programmable interconnection points associated with a node. An experimental setup is proposed to measure the performance parameters such as slack time and power with and without the applied algorithm on the APSoC routing resources. The proposed setup requires no external equipment such as manufactured equipments or external instruments for performance measurement.

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“…In deterministic approach, the inputs are concentrated on an interest region controllably. In [7], and [8], they applied the random approach to characterize the metastability for a Flip-Flop on an FPGA Virtex-4. Similarly, the work in [9] characterized the metastability of Flip-Flips on 65 nm CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

Measurements of metastability in MUTEX on an FPGA

Toan

Tung

Lee

2018

IEICE Electron. Express

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In this paper, we propose a new method for measuring metastability in the mutual exclusion element (MUTEX) implemented on a Field Programmable Gate Array (FPGA). Our method uses fine-grained phase shifts of a digital clock manager to trigger Flip-Flops to generate concurrent inputs for a MUTEX. By dynamically adjusting the phase shift between two clock signals, we can force the MUTEX into a metastable state. The benefit of our approach is that it is easier to force the MUTEX become metastable compared to the conventional approach using two un-correlated signals. The experiments have been performed on a Xilinx Spartan-6 (XC6SLX9-4TQG144C).

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A Programmable Delay Line for Metastability Characterization in FPGAs

Cited by 6 publications

References 8 publications

An Experimental Study of Metastability-Induced Glitching Behavior

An Experimental Study of Metastability-Induced Glitching Behavior

Optimum Reconfiguration of Routing Interconnection Network in APSoC Fabrics

Measurements of metastability in MUTEX on an FPGA

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