A programmable CMOS dual channel interface processor for telecommunications applications

Ahuja, B.K.; Gray, P.R.; Baxter, W.; Uehara, G.T.

doi:10.1109/jssc.1984.1052242

Cited by 36 publications

(10 citation statements)

References 8 publications

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“…This method can achieve highly power-efficient, less-distorted, high-swing common-source output stage. These error amplifiers need to have a relatively low gain to guarantee stable operation of the loop: otherwise, a typical input offset voltage of tens of mV would cause a huge change in the quiescent output current [5,6].…”

Section: From R-stringmentioning

confidence: 99%

58.4: 10‐Bit Column Driver with Split‐DAC Architecture

Woo¹,

Shin²,

Choe³

et al. 2008

Symp Digest of Tech Papers

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An 8‐bit coarse digital‐to‐analog converter (DAC), which adopts both array and tree‐type decoders, is combined with a 2‐bit fine interpolation DAC to reduce RC time delay and die area of a column driver for LCD‐HDTV applications. Error amplifiers drive a pair of column lines in the output buffer to realize rail‐to‐rail voltage swing with a high slew rate. The design has been fabricated in 0.3 μm LV‐HV CMOS technology.

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Section: From R-stringmentioning

confidence: 99%

58.4: 10‐Bit Column Driver with Split‐DAC Architecture

Woo¹,

Shin²,

Choe³

et al. 2008

Symp Digest of Tech Papers

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“…Therefore, the gain is generally around 10 [8]. The circuit diagram of a negative-half amplifier is shown in Fig.…”

Section: Voltage-mode Drivermentioning

confidence: 99%

A 3.3-V Low-Power Compact Driver for Multi-Standard Physical Layer

Park¹,

Lee²,

Jeong³

2007

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies 0.14 mm 2 . Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.

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“…The first push-pull topology to be considered is shown in Fig.5 [5]. The two large common source output transistors M J ' M2 are driven by two amplifiers A J , A 2 .…”

Section: Push-pull Stagesmentioning

confidence: 99%

“…Finally, they must have a reduced gain (typically less than 10). This is due to the input offset of A V } and A V2 • In the case of a large gain this offset can create an unacceptable chip-to-chip variation of the quiescent current level in M} and M 2 • Yin M2 Figure 5: Block diagram of a pseudo source-follower [5].…”

Section: Push-pull Stagesmentioning

confidence: 99%

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CMOS Buffer Amplifiers

Castello

1993

Analog Circuit Design

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This paper gives a tutorial presentation on the design of buffer amplifiers in CMOS technology. These are circuits that must drive a load made up of either a large capacitor or a small resistor or both. The core of the paper deals with special purpose buffer amplifiers intended for a specific application most often within a mixed analOg/digital system integrated on a single chip. Several architectures for both input class NB and output push-pull stages are discussed and compared. Issues like quiescent current control, frequency compensation, open loop and closed loop linearity are analysed in detail with the help of many examples.

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A programmable CMOS dual channel interface processor for telecommunications applications

Cited by 36 publications

References 8 publications

58.4: 10‐Bit Column Driver with Split‐DAC Architecture

58.4: 10‐Bit Column Driver with Split‐DAC Architecture

A 3.3-V Low-Power Compact Driver for Multi-Standard Physical Layer

CMOS Buffer Amplifiers

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