A process-scalable low-power charge-domain 13-bit pipeline ADC

Anthony, Michael P.; Köhler, Elof; Kurtze, J.; Kushner, Lawrence J.; Sollner, G.

doi:10.1109/vlsic.2008.4586015

Cited by 41 publications

(19 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Under ideal PVT conditions, V 0 is almost a constant [1]. In CD pipelined ADCs, two BCTs are employed in a conversion stage to perform differential signal processing [1].…”

Section: Analysis Of the Existing Bctmentioning

confidence: 99%

“…Under ideal PVT conditions, V 0 is almost a constant [1]. In CD pipelined ADCs, two BCTs are employed in a conversion stage to perform differential signal processing [1]. Assuming the input signals of the differential stage are V inp and V inn , the differential charge, Q T,diff , and the common-mode charge, Q T,CM , can be obtained from Eqn.…”

Section: Analysis Of the Existing Bctmentioning

confidence: 99%

“…The charge domain (CD) pipelined ADC based on boosted charge transfer (BCT) circuits is a newly emerging opamp-less ADC architecture [1,2], which can achieve high speed A/D conversion at lower power dissipation compared with those conventional pipelined ADCs based on switched-capacitor architectures [3,4,5]. However, the output charge amount of the BCT in [1,2] is influenced remarkably by process, voltage and temperature (PVT) variations, which can cause large fluctuations in the common-mode charge when the BCTs are used in CD pipelined ADCs.…”

Section: Introductionmentioning

confidence: 99%

“…However, the output charge amount of the BCT in [1,2] is influenced remarkably by process, voltage and temperature (PVT) variations, which can cause large fluctuations in the common-mode charge when the BCTs are used in CD pipelined ADCs. The common-mode charge errors reduce the input signal range of the ADC extensively.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, as common-mode charge error accumulates stage by stage, several stages at the backend of the pipeline may fail to function when common-mode charge error increases to a given extent. In order to solve the problem, complicated common-mode charge control techniques are introduced in [1,2] to stabilize common-mode charge in each stage, which increases the design complexity, chip area and power consumption. This letter presents a new BCT that adopts a differential difference amplifier (DDA) with a differential voltage reference to reject the output common-mode charge errors caused by PVT variations.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A PVT insensitive boosted charge transfer for high speed charge-domain pipelined ADCs

Chen

Zong-guang

Huang

et al. 2012

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:A process, voltage, temperature (PVT) insensitive boosted charge transfer (BCT) circuit for charge-domain (CD) pipelined analog-to-digital converters (ADC) is presented. The output charge of existing BCT varies extensively with PVT variation, leading to large common-mode charge errors in each differential BCT stage when used in CD pipelined ADCs. Therefore, complicate commonmode control circuits must be adopted to stabilize the common-mode charge of each stage, which consumes large power and chip area. The proposed BCT circuit employs a differential difference amplifier and a differential voltage reference to reject the charge errors caused by PVT variations. A 125-MSPS, 10-bit CD pipelined ADC without commonmode control circuit is implemented based on the proposed BCT, consuming only 27 mW from a 1.8 V supply.

show abstract

“…Under ideal PVT conditions, V 0 is almost a constant [1]. In CD pipelined ADCs, two BCTs are employed in a conversion stage to perform differential signal processing [1].…”

Section: Analysis Of the Existing Bctmentioning

confidence: 99%

Section: Analysis Of the Existing Bctmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A PVT insensitive boosted charge transfer for high speed charge-domain pipelined ADCs

Chen

Zong-guang

Huang

et al. 2012

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

Digitally Assisted Analog to Digital Converters

Verbruggen¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

View full text Add to dashboard Cite

show abstract

Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

View full text Add to dashboard Cite

This chapter discusses the architectures of Nyquist rate Analog-toDigital Converters (ADCs), that are embedded in systems-on-chip (SoCs) implementing some of the most widespread mobile communication, wireless and wireline connectivity standards. The typical requirements for these ADCs are presented, and the main conversion architectures are described in terms of the fundamental operations realized inside them. This constitutes a unified treatment that relates all architectures, thus providing a deeper understanding of their fundamental limitations and trade-offs. We then discuss some of the solutions recently published in the literature to improve ADC energy efficiency. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

show abstract

A process-scalable low-power charge-domain 13-bit pipeline ADC

Cited by 41 publications

References 6 publications

A PVT insensitive boosted charge transfer for high speed charge-domain pipelined ADCs

A PVT insensitive boosted charge transfer for high speed charge-domain pipelined ADCs

Digitally Assisted Analog to Digital Converters

Recent Advances and Trends in High-Performance Embedded Data Converters

Contact Info

Product

Resources

About