A Priority-Based Budget Scheduler with Conservative Dataflow Model

Steine, Marcel; Bekooij, Marco; Wiggers, Maarten H.

doi:10.1109/dsd.2009.148

Cited by 27 publications

(34 citation statements)

References 17 publications

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“…The conflict on the shared resource is resolved using priorities, e.g. in Ccsp [2] and Pbs [20] arbiters. Under MBBA arbiter [3], number of priority levels are defined, Gi.…”

Section: Related Workmentioning

confidence: 99%

The Priority Division Arbiter for low WCET and high Resource Utilization in Multi-core Architectures

Shah

Huang²,

Knoll

2014

Proceedings of the 22nd International Conference on Real-Time Networks and Systems

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Shared memory arbiters play a major role in determining the Worst Case Execution Time (Wcet) of applications executing on multi-core architectures. Apart from the produced Wcet, shared memory utilization is another important parameter which characterizes the suitability of an arbiter for a particular system. This paper compares the traditional arbiters, the Static priority (aka fixed priority), the Time Division Multiple Access (Tdma) and the Round robin against the Priority division arbiter on the above mentioned merits. The paper extends the Priority division arbiter by providing a new configuration, called h1, which is highly attractive for mixed critical systems with a single Hard Real-Time (Hrt) application. The paper derives formulas to calculate the worst case latency and the worst case memory utilization. The analysis proves that the Priority division arbiter outperforms the Tdma arbiter in memory utilization and the Round robin arbiter in the produced Wcet. Moreover, the Priority division arbiter, under the h1 mode, outperforms the Static priority arbiter in terms of the produced Wcet of the single Hrt application. The supporting evidences are achieved by conducting experiments on a quad-core NIOS architecture built on Altera Fpga. The test applications are chosen from the Mälardalen Wcet benchmark suit.

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“…The conflict on the shared resource is resolved using priorities, e.g. in Ccsp [2] and Pbs [20] arbiters. Under MBBA arbiter [3], number of priority levels are defined, Gi.…”

Section: Related Workmentioning

confidence: 99%

The Priority Division Arbiter for low WCET and high Resource Utilization in Multi-core Architectures

Shah

Huang²,

Knoll

2014

Proceedings of the 22nd International Conference on Real-Time Networks and Systems

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“…ii) Algorithms for the worst case analysis under advanced arbitration techniques, e.g. Priority Based Budget Scheduler (PBS) [27] and Credit Controlled Static Priority (CCSP) [4] can be used. iii) Minimal modifications to the existing architecture is required.…”

Section: The Basic Techniquementioning

confidence: 99%

Measurement based WCET Analysis for Multi-core Architectures

Shah

Coombes

Raabe

et al. 2014

Proceedings of the 22nd International Conference on Real-Time Networks and Systems

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The interference on shared resources caused by concurrently executing applications unpredictably prolongs their execution. Hence, determination of the Worst Case Execution Time (Wcet) of applications executing on shared memory multi-core processors is hard to estimate. This hinders the adoption of Commercial Off The Shelf (Cots) multicore processors in hard real-time systems. The existing techniques opt for tailored multi-core architectures to provide high computation power at predictable execution time. However, this approach yields poor resource utilization and high costs. In this paper, we present a technique to measure the Wcet of applications on multi-core architectures using existing measurement based timing analysis tools. Our technique has a minor area impact (≈ 5%). However, this impact is limited to the emulation devices only and production chips remain unchanged. Thus, our technique does not impact performance of the Cots chips by any ways. The technique is demonstrated by measuring Wcet of benchmark applications using the RapiTime timing analysis tool. The tests are conducted on a quad-core NIOS II processor on an Altera Fpga.

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“…For instance, priority-based schedulers, such as Credit-Controlled Static Priority (CCSP) [2] and Priority-Budget Scheduling (PBS) [3] allow low latency to bursty requestors, which are users whose request rate fluctuate significantly over time. A linear service guarantee based on the latency-rate (LR) server model [4] cannot capture the bursty service provision by these arbiters.…”

Section: Introductionmentioning

confidence: 99%

“…The over-allocation can be reduced by increasing the number of entries, although, this increases the WCRT of all requestors sharing the resource [2], [15]. Priority Budget Scheduling (PBS) [3] addresses the coupling between latency and rate using priorities. However, it only improves the latency of a single bursty requestor with high priority and still couples allocation granularity and latency.…”

Section: Introductionmentioning

confidence: 99%

Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration

Siyoum

Åkesson

Stuijk

et al. 2011

2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications

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Abstract-A present-day System-on-Chip (SoC) runs a wide range of applications with diverse real-time requirements. Resources, such as processors, interconnects and memories, are shared between these applications to reduce cost. Resource sharing causes temporal interference, which must be bounded by a suitable resource arbiter. System-level analysis techniques use the service guarantee of the arbiter to ensure that realtime requirements of these applications are satisfied. A service guarantee that underestimates the minimum service provided by an arbiter results in more allocation of resources than needed to satisfy latency and throughput requirements. For instance, a linear service guarantee cannot accurately capture bursty service provision by many priority-based schedulers, such as Credit-Controlled Static Priority (CCSP) and Priority-Budget Scheduling (PBS). As a result, the timing analysis of these arbiters becomes too pessimistic. This leads to unnecessary cost penalties since some SoC resources, such as SDRAM bandwidth, are scarce and expensive.

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A Priority-Based Budget Scheduler with Conservative Dataflow Model

Cited by 27 publications

References 17 publications

The Priority Division Arbiter for low WCET and high Resource Utilization in Multi-core Architectures

The Priority Division Arbiter for low WCET and high Resource Utilization in Multi-core Architectures

Measurement based WCET Analysis for Multi-core Architectures

Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration

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