A preamplifier for the muon system of the CBM experiment

Malankin, E.; Shumikhin, V.

doi:10.1134/s0020441214020031

Cited by 6 publications

(2 citation statements)

References 2 publications

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“…The preamplifier prototype for CBM MUCH (MUCH ASIC v.1) was designed, fabricated & tested at lab conditions with GEM prototypes and Fe 55 source [4]. The corresponding boards for functionality tests and for tests with GEMs of the preamplifier prototype are shown in figure 1 consequently on the left and right sides.…”

Section: Jinst 10 C04006mentioning

confidence: 99%

Development of the read-out ASIC for muon chambers of the CBM experiment

Иванов¹,

Ivanov²,

Malankin³

et al. 2015

J. Inst.

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The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e-at 50 pF, power comsumption of 10 mW per channel, 6 bit SAR ADC. The chip includes 8 analog processing chains, each consisting of preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consunption at 50 Msps. The chip also includes the threshold DAC and the digital part.

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Section: Jinst 10 C04006mentioning

confidence: 99%

Development of the read-out ASIC for muon chambers of the CBM experiment

Иванов¹,

Ivanov²,

Malankin³

et al. 2015

J. Inst.

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“…The preamplifier prototype for CBM MUCH (MUCH ASIC v.1) was designed, fabricated and tested [4]. The prototype includes 10 preamplifier channels.…”

Section: Preamplifier Prototypementioning

confidence: 99%

Development of the read-out ASIC for muon chambers

Bulbakov

Гусев

Malankin

et al. 2016

J. Phys.: Conf. Ser.

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The read-out ASIC for silicon drift detectors E Atkin, P Ivanov, A Krivchenko et al. Abstract. A front-end prototype ASIC for muon chambers is presented. ASIC was designed and prototyped in the CMOS UMC MMRF 180 nm process via Europractice. The chip includes 8 analog processing channels, each consisting of a preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consumption at 50 Msps. The chip also includes the threshold DAC and digital serializer. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e-at 50 pF, power consumption of 10 mW per channel, 6 bit SAR ADC.

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