Development of the read-out ASIC for muon chambers of the CBM experiment

Иванов, В. В.; Ivanov, P.; Malankin, E.; Normanov, D.; Osipov, Dmitry; Samsonov, V.; Shumikhin, V.; Voronin, A.

doi:10.1088/1748-0221/10/04/c04006

Cited by 11 publications

(7 citation statements)

References 9 publications

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“…The results of laboratory tests confirmed the functioning of their inherent principles. This year the run of the 8-channel chip [4] was performed, containing the basic building blocks for the system, with the exception of the derandomizer block. The next step is expected to create a 64 channel chip (64 reading channels 8 channels processing) with the derandomizer architecture.…”

Section: Resultsmentioning

confidence: 99%

Architecture of the multichannel data-driven ASIC

Normanov

2016

J. Phys.: Conf. Ser.

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The development architecture of a multichannel data-driven ASIC is presented. It provides the selection of useful events at an early stage of reading out detector signals. The architecture is based on fast cross-point switches of analog signals, followed by their digitization by a limited set of ADCs and high-speed output data serialization. Such approach reduces the number of subsequent ADCs as well as digital processing channels. That leads to lower power consumption and chip area. The results of a prototype ASIC development, based on this architecture and intended for the CBM experiment at FAIR, are given.

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Section: Resultsmentioning

confidence: 99%

Architecture of the multichannel data-driven ASIC

Normanov

2016

J. Phys.: Conf. Ser.

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“…The ENC of the fast and slow shaper outputs are 2000 el and 1500 el correspondently at 50 pF of the equivalent detector capacitance (see figure 7). The schematic of the MUCH ASIC v.2 ADC [5] is shown in figure 8. The single-ended architecture was chosen to save design area.…”

Section: -Channels Asic Prototypementioning

confidence: 99%

Development of the read-out ASIC for muon chambers

Bulbakov

Гусев

Malankin

et al. 2016

J. Phys.: Conf. Ser.

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The read-out ASIC for silicon drift detectors E Atkin, P Ivanov, A Krivchenko et al. Abstract. A front-end prototype ASIC for muon chambers is presented. ASIC was designed and prototyped in the CMOS UMC MMRF 180 nm process via Europractice. The chip includes 8 analog processing channels, each consisting of a preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consumption at 50 Msps. The chip also includes the threshold DAC and digital serializer. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e-at 50 pF, power consumption of 10 mW per channel, 6 bit SAR ADC.

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“…For charge measurement, there are several methods applied in the readout electronics of high energy physics experiments, such as analog peak detection adopted in [4][5][6][7], digital peak detection adopted in [8][9][10][11], Time Over Threshold (TOT) principle adopted in [12][13][14][15], and waveform digitization based on Switched Capacitor Array (SCA) adopted in [16][17][18][19]. The analog peak detection has a relatively large dead time and the resolution of SCAbased waveform digitization is limited with high input signal frequency.…”

Section: Introductionmentioning

confidence: 99%

“…[4][5][6][7], digital peak detection adopted in Refs. [8][9][10][11], the Time Over Threshold (TOT) principle adopted in Refs. [12][13][14][15], and waveform digitization based on a Switched Capacitor Array (SCA) adopted in Refs.…”

Section: Introductionmentioning

confidence: 99%

Design and simulation of a 12-bit, 40 MSPS asynchronous SAR ADC for the readout of PMT signals

Liu

Qin

et al. 2016

Chinese Phys. C

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High precision and large dynamic range measurement are required in the readout systems for the Water Cherenkov Detector Array (WCDA) in Large High Altitude Air Shower Observatory (LHAASO). This paper presents a prototype of 12-bit 40 MSPS Analog-to-Digital Converter (ADC) Application Specific Integrated Circuit (ASIC) designed for the readout of LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on power-efficient Successive Approximation Register (SAR) architecture, which incorporates the key parts such as Capacitive Digital-to-Analog Converter (CDAC), dynamic comparator and asynchronous SAR control logic. The simulation results indicate that the Effective Number Of Bits (ENOB) with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are good enough for the readout requirements of the WCDA.

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Development of the read-out ASIC for muon chambers of the CBM experiment

Cited by 11 publications

References 9 publications

Architecture of the multichannel data-driven ASIC

Architecture of the multichannel data-driven ASIC

Development of the read-out ASIC for muon chambers

Design and simulation of a 12-bit, 40 MSPS asynchronous SAR ADC for the readout of PMT signals

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